Dislocation glide suppression for misfit dislocation free heteroepitaxy

Patent metadata

Field	Value
Publication number	US-11804525-B2
Application number	US-202017066876-A
Country	US
Kind code	B2
Filing date	Oct 9, 2020
Priority date	Oct 11, 2019
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

An epitaxial structure includes a semiconductor substrate, a dislocation blocking layer; and one or more active layers.

First claim

The invention claimed is:

1. An epitaxial structure comprising:
a semiconductor substrate;
a dislocation blocking layer fabricated to include a plurality of pinning points;
one or more active layers;
a threading dislocation extending through the dislocation blocking layer and the one or more active layers, wherein the threading dislocation is glissile; and
a misfit dislocation extending along a plane of the dislocation blocking layer, wherein the threading dislocation incident on one of the plurality of pinning points results in the formation of the misfit dislocation within the dislocation blocking layer but not within the one or more active layers through which the threading dislocation extends.

2. The epitaxial structure of claim 1 , further including a spacer layer located between the dislocation blocking layer and the one or more active layers.

3. The epitaxial structure of claim 2 , wherein a thickness of the dislocation blocking layer is less than a thickness of the spacer layer.

4. The epitaxial structure of claim 3 , wherein the spacer layer thickness is approximately 100 nanometers (nm).

5. The epitaxial structure of claim 1 , wherein the dislocation blocking layer is characterized by either a compressive strain or a tensile strain.

6. The epitaxial structure of claim 1 , wherein the plurality of pinning points associated with the dislocation blocking layer are provided via one or more nanostructure layers fabricated within the dislocation blocking layer.

7. The epitaxial structure of claim 6 , wherein the one or more nanostructure layers includes one or more layers of quantum wells and/or one or more layers of quantum dots.

8. The epitaxial structure of claim 1 , wherein the plurality of pinning points associated with the dislocation blocking layer are provided via alloy hardening, and/or precipitate hardening of the dislocation blocking layer.

9. The epitaxial structure of claim 1 , wherein the dislocation blocking layer comprises a quantum well (QW).

10. The epitaxial structure of claim 9 , wherein the dislocation blocking layer comprises InGaAs and/or InAlAs.

11. An epitaxial structure comprising:
a semiconductor substrate;
a bottom blocking region;
one or more active layers;
a misfit dislocation extending along a plane of the bottom blocking region; and
one or more threading dislocations extending through the bottom blocking region and the one or more active layers, wherein the bottom blocking region is located between the semiconductor substrate and the one or more active layers and wherein a lattice constant of the semiconductor substrate is different than a lattice constant of the one or more active layers, wherein the bottom blocking region includes a dislocation blocking layer and a spacer layer, wherein the spacer layer is located between the dislocation blocking layer and the one or more active layers, wherein the dislocation blocking layer includes pinning points configured to pin the one or more threading dislocations extending through the bottom blocking region and the one or more active layers, wherein the misfit dislocation is formed where the threading dislocation intersects one of the pinning points within the dislocation blocking layer, wherein formation of the misfit dislocation within the dislocation blocking layer prevents misfit dislocation formation within the one or more active layers.

12. The epitaxial structure of claim 11 , further including:
an upper blocking region, wherein the one or more active layers are located between the lower blocking region and the upper blocking region; and
a second misfit dislocation extending along a plane of the upper blocking layer.

13. The epitaxial structure of claim 11 , wherein the dislocation blocking layer comprises a quantum well (QW).

14. The epitaxial structure of claim 13 , wherein the dislocation blocking layer comprises InGaAs and/or InAlAs.

15. An epitaxial structure comprising:
a semiconductor substrate;
one or more active layers;
a first dislocation blocking layer comprising a first plurality of pinning points, the first dislocation blocking layer located below the one or more active layers;
a second dislocation blocking layer comprising a second plurality of pinning points, the second dislocation blocking layer located above the one or more active layers; and
a threading dislocation extending through the one or more active layers and the first and second dislocation blocking layer; and
a first misfit dislocation formed within a plane of the first dislocation blocking layer at an intersection of the threading dislocation and one of the first plurality of pinning points; and
a second misfit dislocation formed within a plane of the second dislocation blocking layer at an intersection of the threading dislocation and one of the second plurality of pinning points.

16. The epitaxial structure of claim 15 , wherein the first dislocation blocking layer and/or second dislocation blocking layer comprises a quantum well (QW).

17. The epitaxial structure of claim 16 , wherein the first dislocation blocking layer and/or the second dislocation blocking layer comprises InGaAs and/or InAlAs.

Assignees

• Univ California

Inventors

• Bowers John
• Norman Justin
• Mukherjee Kunal
• Selvidge Jennifer
• Hughes Eamonn

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3221

  Arsenides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title