Computer processing devices with dynamic shared cache line copy retention policy selection

Patent metadata

Field	Value
Publication number	US-11803473-B2
Application number	US-202117521483-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Nov 8, 2021
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

First claim

What is claimed is:

1. A method comprising:
determining a cache line sharing parameter indicative of a quantity of shared cache lines in a plurality of caches of a first level of a computer processing device; and
setting a shared cache line copy retention policy for a cache of a second level that is coupled to the plurality of caches based on the cache line sharing parameter.

2. The method of claim 1 , wherein determining the cache line sharing parameter comprises:
identifying, based on memory access requests issued by cores of the computer processing device, cache lines requested by more than one of the cores as being first shared cache lines; and
determining the cache line sharing parameter based, at least in part, on the first shared cache lines.

3. The method of claim 2 , wherein determining the cache line sharing parameter further comprises:
identifying, based on cache probes issued by cores of external core complexes, cache lines of the plurality of caches that are requested in the cache probes as being second shared cache lines, wherein the cache line sharing parameter is determined further based on the second shared cache lines.

4. The method of claim 1 , wherein determining the cache line sharing parameter comprises:
determining the cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the cache of the second level, wherein the shadow tags provide a listing of all cache lines in the plurality of caches.

5. The method of claim 1 , wherein determining the cache line sharing parameter comprises:
identifying, based on memory access requests issued by cores of the computer processing device, cache lines requested by more than one of the cores as being first shared cache lines;
determining a first cache line sharing parameter based, at least in part, on the first shared cache lines;
determining a second cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the cache of the second level, wherein the shadow tags provide a listing of all cache lines in the plurality of caches; and
determining the cache line sharing parameter as an average of the first cache line sharing parameter and the second cache line sharing parameter.

6. The method of claim 1 , wherein the shared cache line copy retention policy for the cache of the second level determines whether copies of shared cache lines of the plurality of caches are retained in the cache of the second level.

7. A method comprising:
implementing set dueling in a core complex of a computer processing device to select a shared cache line copy retention policy for a set of caches of a first level and a cache of a second level.

8. The method of claim 7 , wherein implementing the set dueling comprises:
allocating a first dedicated set of cache line indices for use in conjunction with a first shared cache line copy retention policy;
allocating a second dedicated set of cache line indices for use in conjunction with a second shared cache line copy retention policy; and
tracking cache misses associated with the cache of the second level and cache-to-cache (C2C) transfers associated with each of the first dedicated set and the second dedicated set, separately, using a counter; and
configuring, based on the counter, the cache of the second level to use one of the first shared cache line copy retention policy and second first shared cache
line copy retention policy for one or more follower sets of cache line indices.

9. The method of claim 8 , wherein the first dedicated set of cache line indices, the second dedicated set of cache line indices, and the one or more follower sets of cache line indices are cache line indices of the set of caches of a first level of the core complex.

10. The method of claim 8 , wherein the first dedicated set of cache line indices, the second dedicated set of cache line indices, and the one or more follower sets of cache line indices are cache line indices of the cache of the second level.

11. The method of claim 8 , wherein the first shared cache line copy retention policy causes the cache of the second level to retain copies of shared cache lines of the set of caches of a first level of the core complex, and the second shared cache line copy retention policy causes the cache of the second level to not retain copies of shared cache lines of the set of caches of the first level.

12. A computer processing device comprising:
a set of caches of a first level; and
a cache of a second level coupled to the set of caches of the first level, the computer processing device being configured to dynamically select a shared cache line copy retention policy that determines whether shared cache lines of at least one cache of the set of caches of the first level are retained in the cache of the second level.

13. The computer processing device of claim 12 , further comprising:
sharing detection logic configured to determine a cache line sharing parameter indicative of a quantity of shared cache lines in the at least one cache of the set of caches of the first level, wherein the cache of the second level is configured to dynamically select the shared cache line copy retention policy based on the cache line sharing parameter.

14. The computer processing device of claim 13 , further comprising:
a plurality of processor cores coupled to the set of caches of the first level, wherein the sharing detection logic is configured to:
identify, based on memory access requests issued by any of the plurality of processor cores, cache lines of the at least one cache of the set of caches of the first level that are requested by more than one of the plurality of processor cores as being first shared cache lines; and
determine the cache line sharing parameter based, at least in part, on a quantity of the first shared cache lines.

15. The computer processing device of claim 13 , wherein the sharing detection logic is configured to determine the cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the cache of the second level, wherein the shadow tags provide a listing of all cache lines in the set of caches of the first level.

16. The computer processing device of claim 12 , further comprising:
a set dueling module configured to implement a set dueling mechanism in the computer processing device, wherein the cache of the second level is configured to dynamically select the shared cache line copy retention policy based on a counter associated with the set dueling mechanism.

17. The computer processing device of claim 16 , wherein the set dueling module is configured to:
allocate a first dedicated set of cache line indices for use in conjunction with a first shared cache line copy retention policy;
allocate a second dedicated set of cache line indices for use in conjunction with a second shared cache line copy retention policy; and
track cache misses associated with the cache of the second level and cache-to-cache (C2C) transfers associated with each of the first dedicated set and the second dedicated set, separately, using the counter, wherein the cache of the second level is configured to select, based on the counter, one of the first shared cache line copy retention policy and second first shared cache line copy retention policy to be used for one or more follower sets of cache line indices.

18. The computer processing device of claim 17 , wherein the first dedicated set of cache line indices, the second dedicated set of cache line indices, and

Assignees

• Advanced Micro Devices Inc

Inventors

• Kelley John
• Moyer Paul

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/502

  using adaptive policy · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title