Sensor processing system, sensor system, and sensor processing method

Patent metadata

Field	Value
Publication number	US-11802885-B2
Application number	US-202016862210-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Apr 30, 2019
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

A sensor processing system includes a plurality of reduction circuits. The plurality of reduction circuits correspond to a plurality of sensors on a one-to-one basis. Each of the plurality of reduction circuits is electrically connected to an output terminal of a corresponding one of the plurality of sensors to reduce a low-frequency component of a sensor output of the corresponding one of the plurality of sensors.

First claim

The invention claimed is:

1. A sensor processing system, comprising:
a plurality of reduction circuits,
the plurality of reduction circuits corresponding to a plurality of sensors on a one-to-one basis, each of the plurality of sensors measuring the same physical quantity,
each of the plurality of reduction circuits being directly connected to an output terminal of a corresponding one of the plurality of sensors to reduce a low-frequency component of a sensor output of the corresponding one of the plurality of sensors,

a comparator configured to receive, as an input signal, outputs of two reduction circuits of the plurality of reduction circuits, and compare the outputs of the two reduction circuits of the plurality of reduction circuits with each other to output a comparison result, the outputs of the two reduction circuits being directly connected to the comparator; and
a control circuit configured to determine, based on the comparison result, that is output from the comparator, whether or not the two sensors of the plurality of sensors corresponding to the two reduction circuits of the plurality of reduction circuits providing the input signals to the comparator are operating normally.

2. The sensor processing system of claim 1 , wherein the plurality of sensors are angular rate sensors.

3. The sensor processing system of claim 1 , wherein the plurality of sensors are acceleration sensors.

4. The sensor processing system of claim 1 , wherein each of the plurality of reduction circuits is branched from an output path of the corresponding one of the plurality of sensors.

5. The sensor processing system of claim 4 , further comprising an adder configured to add up sensor outputs of the plurality of sensors to output an addition result.

6. The sensor processing system of claim 1 , wherein each of the plurality of reduction circuits is inserted in an output path of the corresponding one of the plurality of sensors.

7. The sensor processing system of claim 6 , further comprising an adder configured to add up outputs of the plurality of reduction circuits to output an addition result.

8. The sensor processing system of claim 5 , wherein the adder is configured to set individual contribution factors for the plurality of sensors.

9. The sensor processing system of claim 7 , wherein the adder is configured to set individual contribution factors for the plurality of sensors.

10. A sensor system, comprising:
the sensor processing system of claim 1 ; and
the plurality of sensors.

11. The sensor processing system of claim 1 , wherein each of the plurality of reduction circuits includes at least one of a high-pass filter or a band-pass filter.

12. The sensor processing system of claim 1 , wherein low-frequency component of each of the outputs of the two reduction circuits being reduced.

13. A sensor processing system, comprising:
a plurality of reduction circuits,
the plurality of reduction circuits corresponding to a plurality of sensors on a one-to-one basis,
each of the plurality of reduction circuits being electrically connected to an output terminal of a corresponding one of the plurality of sensors to reduce a low-frequency component of a sensor output of the corresponding one of the plurality of sensors;
a comparator configured to receive, as an input signal, outputs of two reduction circuits of the plurality of reduction circuits, and compare the outputs of the two reduction circuits of the plurality of reduction circuits with each other to output a comparison result;
a control circuit configured to determine, based on the comparison result, whether or not the corresponding one of the plurality of sensors is normal; and
an adder configured to add up sensor outputs of the plurality of sensors to output an addition result, wherein
each of the plurality of reduction circuits is branched from an output path of the corresponding one of the plurality of sensors,
the adder is configured to set individual contribution factors for the plurality of sensors, and decrease a contribution factor for an anomalous sensor of the plurality of sensors based on the comparison result by the comparator.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Yamada Kouhei

Classifications

• G01P3/4802 Primary

  by using electronic circuits in general · CPC title

• G01R23/005

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing phase or frequency of 2 mutually independent oscillations in demodulators) · CPC title

• G01P15/0802 Primary

  Details · CPC title