Flash memory device used in neuromorphic computing system

Patent metadata

Field	Value
Publication number	US-11800705-B2
Application number	US-202117538747-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	Jun 7, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.

First claim

What is claimed is:

1. A flash memory device comprising:
a substrate;
a channel layer disposed on the substrate and made of a two-dimensional material;
a source and a drain disposed at both ends of the channel layer;
a tunneling insulating layer disposed on the channel layer and having a first dielectric constant;
a floating gate disposed on the tunneling insulating layer and made of a two-dimensional material;
a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant; and
an upper gate disposed on the blocking insulating layer;
wherein a thickness of the blocking insulating layer is greater than a thickness of the tunneling insulating layer,
wherein the channel layer includes at least one of MoS 2 , MoSe 2 , WSe 2 , and WS 2 , and the floating gate includes at least one of graphene, graphene oxide, carbon nanotube, and MoS 2 ,
wherein the tunneling insulating layer includes at least one of SiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 , and h-BN, and
the blocking insulating layer includes at least one of Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 , and h-BN, and
wherein the MoS 2 is a few-layered MoS 2 , and an energy bandgap and electron affinity are about 1.2 and 4.3 eV for the few-layered MoS 2 , 6.8 and 1.35 eV for the Al 2 O 3 , and 5.25 and 2.0 eV for the HfO 2 , respectively.

2. The flash memory device of claim 1 , wherein the channel layer is formed using a metal organic chemical vapor deposition (MOCVD) process.

3. The flash memory device of claim 1 , wherein the thickness of the blocking insulating layer is about 20 nm and the thickness of the tunneling insulation layer is about 10 nm.

4. The flash memory device of claim 1 , wherein the source and the drain are formed of a Ti electrode and an Au electrode formed by an electron beam deposition process.

5. The flash memory device of claim 4 , wherein the Ti electrode is an adhesive layer.

6. The flash memory device of claim 1 , wherein the tunneling insulating layer is formed by an atomic layer lamination process.

7. The flash memory device of claim 1 , wherein the floating gate is formed by chemical vapor deposition (CVD) process.

Assignees

• Korea Inst Sci & Tech

Inventors

• Kwak Joon Young
• Park Eunpyo
• Lee Suyoun
• Kim Inho
• Park Jong-Keuk
• Kim Jaewook
• Park Jongkil
• Jeong Yeonjoo

Classifications

• H10D64/608

  being superconducting · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title