Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

Patent metadata

Field	Value
Publication number	US-11799483-B2
Application number	US-202117516233-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Feb 9, 2018
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled.

First claim

The invention claimed is:

1. A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, the cell logic structure comprising:
a CMOS gate circuit;
a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and
a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage;
wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled; and

wherein:
the header and footer circuits are configured for disabling the feedback by overdriving the gates of the first header transistor and the first footer transistor.

2. The cell logic structure of claim 1 , wherein:
the first and second header transistors comprise NMOS transistors and the first and second footer transistors comprise PMOS transistor.

3. The cell logic structure of claim 1 , wherein the first and second header transistors comprise NMOS transistors.

4. The cell logic structure of claim 1 , wherein the first and second footer transistors comprise PMOS transistors.

5. A method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, the method comprising the steps of:
controlling a header circuit coupled to a CMOS gate circuit, the header circuit comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit, and
controlling a footer circuit coupled to the CMOS gate circuit, the footer circuit comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage;
such that the multi-mode system is switchable between different operation modes, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled; and

wherein:
the header and footer circuits are configured for disabling the feedback by overdriving the gates of the first header transistor and the first footer transistor.

6. The method of claim 5 , wherein:
the first and second header transistors comprise NMOS transistors and the first and second footer transistors comprise PMOS transistors.

7. The method of claim 5 , wherein the first and second header transistors comprise NMOS transistors.

8. The method of claim 5 , wherein the first and second footer transistors comprise PMOS transistors.

Assignees

• Nat Univ Singapore
• Nat Universty Of Singapore

Inventors

• Lin Longyang
• Jain Saurabh
• Alioto Massimo

Classifications

• H03K19/0948 Primary

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K17/161

  in field-effect transistor switches · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/0185 Primary

  using field effect transistors only · CPC title