Short circuit protection

Patent metadata

Field	Value
Publication number	US-11799281-B2
Application number	US-202117514774-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	May 4, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.

First claim

What is claimed is:

1. An apparatus, comprising:
a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate;
a current sense component coupled to the power switch;
a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component;
an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate; and
an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate, wherein the VOUT clamp includes:
a bi-polar junction transistor (BJT) having a collector, an emitter, and a base, the base configured to receive a reference voltage, and the emitter coupled to the power switch drain,
a first field effect transistor (FET) having a first FET drain, a first FET gate, and a first FET source, the first FET gate coupled to the collector, and the first FET source coupled to the collector through a first resistor;
a second FET having a second FET drain, a second FET source, and a second FET gate, wherein the second FET drain and the second FET gate is coupled to the first FET drain, and the second FET source is coupled to a ground terminal;
a third FET having a third FET drain, a third FET source, and a third FET gate, wherein the third FET gate is coupled to the first FET drain, the third FET drain is coupled to the power switch gate, and the third FET source is coupled to the ground terminal; and
a fourth FET having a fourth FET drain, a fourth FET source, and a fourth FET gate, wherein the fourth FET gate is coupled to the collector, the fourth FET source is coupled to the collector through the first resistor, and the fourth FET drain is coupled to the ground terminal through a second resistor, wherein a negative output detection signal is provided at the fourth FET drain.

2. The apparatus of claim 1 , wherein the current sense component is a FET having a gate coupled to the power switch gate, and a source coupled to the power switch source, the current sense component having a size that is a reduced scale of a size of the power switch.

3. The apparatus of claim 1 , wherein the current limiting circuit includes:
a first error amplifier having a first inverting input, a first non-inverting input, and a first error amplifier output, wherein the first inverting input is coupled to the power switch drain, and the first non-inverting input is coupled to the current sense component;
a fifth FET having a fifth FET drain coupled to the current sense component, a fifth FET gate coupled to the first error amplifier output, and a fifth FET source coupled to the ground terminal through a third resistor; and
a second error amplifier having a second inverting input, a second non-inverting input, and a second error amplifier output, the second non-inverting input coupled to the FET source, the second inverting input configured to receive the reference voltage, and the second error amplifier output configured to provide a gate control signal.

4. The apparatus of claim 1 , wherein the OCP circuit includes:
a fifth FET ) having a fifth FET drain, a fifth FET gate, and a fifth FET source, wherein the fifth FET drain is coupled to the power switch drain, the fifth FET gate is coupled to the power switch gate, and the fifth FET source is coupled to the power switch source through resistor;
a sixth FET having a sixth FET drain, a sixth FET source, and a sixth FET gate, wherein the sixth FET source is coupled to the fifth FET source, and the sixth FET gate and the sixth FET drain are coupled to the ground terminal through a first current source;
a seventh FET having a seventh FET drain, a seventh FET source, and a seventh FET gate, wherein the seventh FET source is coupled to the power switch source through a third resistor, the seventh FET gate is coupled to the ground terminal through the first current source, and the seventh FET drain is coupled to the ground terminal through a second current source;
an eighth FET having an eighth FET drain, an eighth FET source, and an eighth FET gate, wherein the eighth FET source is coupled to the power switch source, and the eighth FET gate is coupled to the seventh FET drain;
a ninth FET having a ninth FET drain, a ninth FET source, and a ninth FET gate, wherein the ninth FET source is coupled to the eighth FET drain, and the ninth FET gate is coupled to the eighth FET drain;
a tenth FET having a tenth FET drain, a tenth FET source, and a tenth FET gate, wherein the tenth FET drain is coupled to the ninth FET drain, the tenth FET gate is coupled to the seventh FET drain, and the tenth FET source is coupled to the ground terminal; and
an inverter having an inverter input coupled to the tenth FET drain and an inverter output configured to provide an OCP detection signal.

5. The apparatus of claim 4 , wherein the inverter is a first inverter, and the OCP circuit includes:
a second inverter having a second inverter input and a second inverter output, wherein the second inverter input is configured to receive the negative output detection signal;
a logical AND circuit having a first AND input, a second AND input, and an AND output, wherein the first AND input is coupled to the second inverter output, and the second AND input is coupled to the inverter output;
a third inverter having a third inverter input and a third inverter output, wherein the third inverter input is coupled to the inverter output;
a transmission gate having a transmission gate input, a transmission gate output, a transmission gate control input, and a transmission gate inverted control input, wherein the transmission gate input is configured to receive a gate control signal, the transmission gate output is coupled to the power switch gate, and the transmission gate inverted control input is coupled to the inverter output;
a fourth inverter having a fourth inverter input and a fourth inverter output, wherein the fourth inverter input is coupled to the inverter output, and the fourth inverter output is coupled to the transmission gate control input;
an eleventh FET having an eleventh FET drain, an eleventh FET source, and an eleventh FET gate, wherein the eleventh FET drain is coupled to the power switch source, the eleventh FET gate is coupled to the AND output, and the eleventh FET source is coupled to the power switch gate through a fourth resistor; and
a twelfth FET having a twelfth FET drain, a twelfth FET source, and a twelfth FET gate, wherein the twelfth FET gate is coupled to the third inverter output, the twelfth FET source is coupled to the power switch source, and the twelfth FET drain is coupled to the power switch gate through the fourth resistor.

6. The apparatus of claim 5 , further comprising a gate driver having a driver input and a driver output, wherein the driver input is configured to receive a signal for driving the power switch, and the driver output is coupled to the transmission gate input.

7. The apparatus of claim 1 , wherein:
the current limiting circuit is a servo-loop based current limit controller configured to control the power switch to regulate a value of an output current (IOUT) of the apparatus with respect to a first threshold;
the OCP circuit is configured to control the power switch to regulate the value of IOUT with respect to a second threshold that is greater than the first threshold; and
the VOUT clamp is configured to control the power switch to maintain a value of the output voltage greater than a third threshold that has a negative value.

8. An apparatus, comprising:
a power switch configured to provide power to a load;
a current limiting circuit coupled to the power switch, wherein the current limitin

Assignees

• Texas Instruments Inc

Inventors

• Kim Eung Jung
• Qu Wenchao

Classifications

• H02H3/08 Primary

  responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

• H02H1/06

  Arrangements for supplying operative power {(power supply arrangements in general G05F, H02M)} · CPC title

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title