Semiconductor package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11798909-B2
Application number	US-202117385991-A
Country	US
Kind code	B2
Filing date	Jul 27, 2021
Priority date	Aug 4, 2020
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a first dielectric layer, which has a first surface and a second surface arranged opposite to each other;
a first patterned conductive layer, which is disposed on the second surface of the first dielectric layer;
an integrated chip, which is embedded in the first dielectric layer, comprising:
a control chip, which has an active surface and a rear surface, and the rear surface being facing the second surface of the first dielectric layer; and
a first power chip, which is a High-Side MOSFET and has a first front surface with a first electrode layout and a first rear surface with a second electrode layout, wherein the first power chip is electrically connected and adhered to the first patterned conductive layer through a first conductive adhesive part by the second electrode layout;
a second power chip, which is a Low-Side MOSFET embedded in the first dielectric layer, and has a second front surface with a third electrode layout and a second rear surface with a fourth electrode layout, wherein the second power chip is electrically connected and adhered to the first patterned conductive layer through a second conductive adhesive part by the fourth electrode layout;
a second patterned conductive layer, which is disposed on the first surface of the first dielectric layer and is electrically connected to the first electrode layout of the first power chip and the third electrode layout of the second power chip through a plurality of first conductive connecting elements;
a plurality of second conductive connecting elements, which are electrically connected between the first patterned conductive layer and the second patterned conductive layer; and
a build-up circuit structure, which is disposed on the first surface of the first dielectric layer and is electrically connected to the second patterned conductive layer.

2. The semiconductor package structure of claim 1 , wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip and includes a gate and a source respectively, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and includes a drain respectively.

3. The semiconductor package structure of claim 2 , wherein the source of the first power chip is electrically connected to the drain of the drain of the second power chip via one of the first conductive connecting elements, the second patterned conductive layer, one of the second conductive connecting elements, the first patterned conductive layer and the first conductive adhesive part.

4. The semiconductor package structure of claim 1 , wherein the first electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and includes a gate and a source respectively, and the second electrode layout of the first power chip is the same as the third electrode layout of the second power chip and includes a drain respectively.

5. The semiconductor package structure of claim 4 , wherein the source of the first power chip is electrically connected to the drain of the second power chip through two of the first conductive connecting elements and the second patterned conductive layer.

6. The semiconductor package structure of claim 1 , wherein the control chip is a driver chip and the active surface is provided with at least one connecting pad, and the second patterned conductive layer is electrically connected to the connecting pad via one of the first conductive connecting elements.

7. The semiconductor package structure of claim 1 , wherein the build-up circuit structure comprising:
a second dielectric layer, which has a third surface and a fourth surface arranged opposite to each other, and is connected to the first surface of the first dielectric layer by the fourth surface; and
a third patterned conductive layer, which is disposed on the third surface of the second dielectric layer and is electrically connected to the second patterned conductive layer through a plurality of third conductive connecting elements.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/09 Primary

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title