Test apparatus, computer readable medium, and test method

Patent metadata

Field	Value
Publication number	US-11797738-B2
Application number	US-202117542039-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Jul 25, 2019
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A design management apparatus ( 100 ) includes a conversion unit ( 12 ) and a test unit ( 13 ). The conversion unit ( 12 ) generates model information ( 403 ) that is a format of design information ( 303 ) being converted, the design information ( 303 ) being the design information ( 303 ) created in a process of mechanical design in an engineering chain, and generates model information ( 405 ) that is a format of design information ( 305 ) being converted, the design information ( 305 ) being the design information ( 305 ) created in a process of control design in the engineering chain. The test unit ( 13 ) associates the model information ( 403 ) and the model information ( 405 ) using entire reference information ( 22 ) that associates the model information ( 403 ) and the model information ( 405 ), and tests for consistency between the model information ( 403 ) and the model information ( 405 ) associated.

First claim

The invention claimed is:

1. A test apparatus comprising:
processing circuitry, wherein
the processing circuitry
converts formats of a plurality of pieces of design information, the plurality of pieces of design information being the design information created in each process of a plurality of processes in an engineering chain, to a format that can be compared between the pieces of design information, generates model information that indicates the design information, the format of which has been converted, for each piece of the design information,
associates a plurality of pieces of model information using entire reference information, the entire reference information being information that associates the plurality of pieces of design information, and tests for consistency between the pieces of model information associated, wherein
the processing circuitry further:
converts, using a conversion rule for format conversion, the formats of the plurality of pieces of design information to a format that can be compared with one another, and
generates each piece of model information in the plurality of pieces of model information from a corresponding one of the plurality of pieces of design information, by converting the format of the corresponding one of the plurality of pieces of design information according to the conversion rule.

2. The test apparatus according to claim 1 , wherein
the processing circuitry
associates, with regard to the internal data that indicates data internally included in the model information, the pieces of internal data included internally in the model information with one another using internal reference information in which correspondence between the pieces of internal data is written, and
tests whether or not first model information that indicates the model information in which the pieces of internal data are associated with one another and second model information that indicates the model information associated with the first model information using the entire reference information are consistent.

3. The test apparatus according to claim 2 , wherein the processing circuitry
determines, at a time of testing consistency between one piece of model information having a plurality of elements and another piece of model information having a plurality of elements, whether or not the element that the one piece of model information has and the element that the another piece of model information has are consistent, and in a case where the processing circuitry determines that the element that the one piece of model information has and the element that the another piece of model information has are not consistent, outputs the element determined as not consistent.

4. The test apparatus according to claim 1 , wherein the processing circuitry
determines, at a time of testing consistency between one piece of model information having a plurality of elements and another piece of model information having a plurality of elements, whether or not the element that the one piece of model information has and the element that the another piece of model information has are consistent, and in a case where the processing circuitry determines that the element that the one piece of model information has and the element that the another piece of model information has are not consistent, outputs the element determined as not consistent.

5. A non-transitory computer readable medium storing a test program causing a computer to execute:
a conversion process to convert formats of a plurality of pieces of design information, the plurality of pieces of design information being the design information created in each process of a plurality of processes in an engineering chain, to a format that can be compared between the pieces of design information, and to generate model information that indicates the design information, the format of which has been converted, for each piece of the design information; and
a test process to associate a plurality of pieces of model information using entire reference information, the entire reference information being information that associates the plurality of pieces of design information, and to test for consistency between the pieces of model information associated, wherein
the conversion process further:
converts, using a conversion rule for format conversion, the formats of the plurality of pieces of design information to a format that can be compared with one another, and
generates each piece of model information in the plurality of pieces of model information from a corresponding one of the plurality of pieces of design information, by converting the format of the corresponding one of the plurality of pieces of design information according to the conversion rule.

6. A test method comprising:
converting formats of a plurality of pieces of design information, the plurality of pieces of design information being the design information created in each process of a plurality of processes in an engineering chain, to a format that can be compared between the pieces of design information,
generating model information that indicates the design information, the format of which has been converted, for each piece of the design information, and
by associating a plurality of pieces of model information using entire reference information, the entire reference information being information that associates the plurality of pieces of design information, testing for consistency between the pieces of model information associated, wherein
converting formats of the plurality of pieces of design information comprises using a conversion rule for format conversion to convert the formats of the plurality of pieces of design information to a format that can be compared with one another, and
generating the model information comprises generating each piece of model information in the plurality of pieces of model information from a corresponding one of the plurality of pieces of design information, by converting the format of the corresponding one of the plurality of pieces of design information according to the conversion rule.

Assignees

• Mitsubishi Electric Corp

Inventors

• Otake Yuya
• Noguchi Satoshi

Classifications

• G06F30/3308 Primary

  using simulation · CPC title

• G06F30/10 Primary

  Geometric CAD · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title