Security chip with resistance to external monitoring attacks

Patent metadata

Field	Value
Publication number	US-11797683-B2
Application number	US-202117382333-A
Country	US
Kind code	B2
Filing date	Jul 21, 2021
Priority date	Dec 4, 2009
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A method for performing a security chip protocol comprises receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware determines a path through a key tree based at least in part on the message. The processing hardware derives a validator at least in part from the secret value using a sequence of entropy redistribution operations associated with the path through the key tree. The processing hardware exchanges the validator between the security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

First claim

What is claimed is:

1. A method for performing a security chip protocol, the method comprising:
receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol;
retrieving, by the processing hardware, a secret value from secure storage hardware operatively coupled to the processing hardware;
determining a path through a key tree based at least in part on the message, wherein the key tree comprises a plurality of nodes and one or more branches connected to each of the plurality of nodes, wherein each of the plurality of nodes are associated with a key and each of the one or more branches are associated with an entropy redistribution operation that, when applied to the key, generates an associated derived key;
deriving, by the processing hardware, a validator at least in part from the secret value using a sequence of entropy redistribution operations and corresponding derived keys associated with the path through the key tree; and
exchanging the validator between the security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

2. The method of claim 1 , wherein the message comprises a message identifier, and wherein the path is determined based at least in part on the message identifier.

3. The method of claim 2 , wherein the path comprises a plurality of portions, the method further comprising:
decomposing the message identifier into a plurality of parts; and
determining each portion of the plurality of portions of the path using one of the plurality of parts of the message identifier.

4. The method as in claim 3 , wherein each portion of the plurality of portions of the path is associated with a distinct entropy redistribution operation.

5. The method as in claim 1 , further comprising:
generating an expected response by the first device;
comparing, at the first device, the validator to the expected response;
determining, by the first device, whether the validator matches the expected response; and
verifying at the first device that the security chip is authentic responsive to the validator matching the expected response.

6. The method of claim 1 , wherein the security chip protocol corresponds to performing a secure transaction, and wherein the message comprises transaction data.

7. The method of claim 1 , wherein the first device comprises at least one of a subscriber identity module (SIM) card or a transit pass.

8. The method of claim 1 , wherein the security chip protocol corresponds to at least one of an authentication procedure between a set-top box and the security chip, a verification procedure for a network login, or access to one or more television signals.

9. A security chip, comprising:
secure storage hardware to store a secret value; and
processing hardware operatively coupled to the secure storage hardware, wherein the processing hardware is to:
receive a message from a first device as part of a security chip protocol;
retrieve the secret value from the secure storage hardware;
determine a path through a key tree based at least in part on the message, wherein the key tree comprises a plurality of nodes and one or more branches connected to each of the plurality of nodes, wherein each of the plurality of nodes are associated with a key and each of the one or more branches are associated with an entropy redistribution operation that, when applied to the key, generates an associated derived key;
derive a validator at least in part from the secret value using a sequence of entropy redistribution operations and corresponding derived keys associated with the path through the key tree; and
provide the validator to the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

10. The security chip of claim 9 , wherein the message comprises a message identifier, and wherein the path comprises a plurality of portions and is determined based at least in part on the message identifier, wherein the processing hardware is further to:
decomposing the message identifier into a plurality of parts; and
determining each portion of the plurality of portions of the path using one of the plurality of parts of the message identifier.

11. The security chip of claim 9 , wherein the security chip protocol corresponds to performing a secure transaction, and wherein the message comprises transaction data.

12. The security chip of claim 9 , wherein the first device comprises at least one of a subscriber identity module (SIM) card or a transit pass.

13. The security chip of claim 9 , wherein the security chip protocol corresponds to at least one of an authentication procedure between a set-top box and the security chip, a verification procedure for a network login, or access to one or more television signals.

14. A system comprising:
a security chip comprising secure storage hardware and processing hardware operatively coupled to the secure storage hardware, wherein the secure storage hardware is to store a secret value and the processing hardware is to:
receive a message from a first device as part of a security chip protocol;
retrieve the secret value from the secure storage hardware;
determine a path through a key tree based at least in part on the message, wherein the key tree comprises a plurality of nodes and one or more branches connected to each of the plurality of nodes, wherein each of the plurality of nodes are associated with a key and each of the one or more branches are associated with an entropy redistribution operation that, when applied to the key, generates an associated derived key;
derive a validator at least in part from the secret value using a sequence of entropy redistribution operations and corresponding derived keys associated with the path through the key tree; and
exchange the validator between the first device security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

15. The system of claim 14 , wherein the security chip protocol corresponds to performing a secure transaction, and wherein the message comprises transaction data.

16. The system of claim 14 , wherein the first device comprises at least one of a subscriber identity module (SIM) card or a transit pass.

17. The system of claim 14 , wherein the security chip protocol corresponds to at least one of an authentication procedure between a set-top box and the security chip, a verification procedure for a network login, or access to one or more television signals.

Assignees

• Cryptography Res Inc

Inventors

• Kocher Paul C
• Rohatgi Pankaj
• Jaffe Joshua M

Classifications

• G06F21/575 Primary

  Secure boot · CPC title

• G06F8/71

  Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F12/1408

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F21/556

  involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title