Read disturb checking method, memory storage device and memory control circuit unit

Patent metadata

Field	Value
Publication number	US-11797222-B2
Application number	US-202217577012-A
Country	US
Kind code	B2
Filing date	Jan 17, 2022
Priority date	Dec 20, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.

First claim

What is claimed is:

1. A read disturb checking method, configured for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical unit groups, each of the plurality of physical unit groups comprises a plurality of physical erasing units, each of the plurality of physical erasing units comprises a plurality of physical programming units, the plurality of physical unit groups comprise a first physical unit group, and the method comprises:
performing a read operation on the plurality of physical programming units;
updating a first read count and a second read count of the first physical unit group according to a total read count of the read operation performed on the plurality of physical programming units in the first physical unit group;
determining whether the first read count is greater than a first read count threshold, and scanning at least one first physical programming unit in the currently read physical erasing unit in response to determining that the first read count is greater than the first read count threshold to obtain a first error bit amount;
determining whether the second read count is greater than a second read count threshold, and scanning all of the plurality of physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining that the second read count is greater than the second read count threshold to obtain a second error bit amount, wherein the second read count threshold is greater than the first read count threshold; and
performing a read disturb prevention operation according to at least one of the first error bit amount and the second error bit amount.

2. The read disturb checking method of claim 1 , wherein the step of scanning all of the plurality of physical programming units in the at least one first physical erasing unit in the first physical unit group to obtain the second error bit amount comprises:
obtaining an index corresponding to the first physical unit group, wherein the index reflects the physical erasing unit to be scanned in the first physical unit group; and
scanning all of the plurality of physical programming units in the at least one first physical erasing unit corresponding to the index according to an indication of the index to obtain the second error bit amount.

3. The read disturb checking method of claim 2 , wherein the method further comprises:
corresponding the index to the next physical erasing unit to be scanned after all of the plurality of physical programming units in the at least one first physical erasing unit are finished scanning.

4. The read disturb checking method of claim 1 , wherein the method further comprises:
updating a third read count of the first physical unit group according to a total read count of the read operation performed on the plurality of physical programming units in the first physical unit group; and
selecting the physical erasing unit that is not scanned in the first physical unit group for scanning when it is determined that the second read count is greater than the second read count threshold to scan at least one first physical erasing unit in the first physical unit group in response to determining that the third read count is not greater than a third read count threshold.

5. The read disturb checking method of claim 1 , wherein the method further comprises:
calculating a scan average according to the second read count threshold and a number of the plurality of physical programming units in the first physical unit group; and
generating the first read count threshold randomly according to the scan average.

6. The read disturb checking method of claim 1 , wherein the step of performing the read disturb prevention operation comprises:
determining whether the first error bit amount is greater than a first error threshold; and
copying a data stored in the currently read physical erasing unit to other physical erasing units in response to determining that the first error bit amount is greater than the first error threshold.

7. The read disturb checking method of claim 1 , wherein the step of performing the read disturb prevention operation comprises:
determining whether the second error bit amount is greater than a second error threshold; and
copying a data stored in the at least one first physical erasing unit to other physical erasing units in response to determining that the second error bit amount is greater than the second error threshold.

8. A memory storage device, comprising:
a connection interface unit configured to be coupled to a host system;
a rewritable non-volatile memory module comprising a plurality of physical unit groups, wherein each of the plurality of physical unit groups comprises a plurality of physical erasing units, each of the plurality of physical erasing units comprises a plurality of physical programming units, and the plurality of physical unit groups comprise a first physical unit group; and
a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to perform a read operation on the plurality of physical programming units,
the memory control circuit unit is further configured to update a first read count and a second read count of the first physical unit group according to a total read count of the read operation performed on the plurality of physical programming units in the first physical unit group,
the memory control circuit unit is further configured to determine whether the first read count is greater than a first read count threshold, and scan at least one first physical programming unit in the currently read physical erasing unit in response to determining that the first read count is greater than the first read count threshold to obtain a first error bit amount,
the memory control circuit unit is further configured to determine whether the second read count is greater than a second read count threshold, and scan all of the plurality of physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining that the second read count is greater than the second read count threshold to obtain a second error bit amount, wherein the second read count threshold is greater than the first read count threshold, and
the memory control circuit unit is further configured to perform a read disturb prevention operation according to at least one of the first error bit amount and the second error bit amount.

9. The memory storage device of claim 8 , wherein the memory control circuit unit is further configured to obtain an index corresponding to the first physical unit group, wherein the index reflects the physical erasing unit to be scanned in the first physical unit group, and
the memory control circuit unit is further configured to scan all of the plurality of physical programming units in the at least one first physical erasing unit corresponding to the index according to an indication of the index to obtain the second error bit amount.

10. The memory storage device of claim 9 , wherein the memory control circuit unit is further configured to correspond the index to the next physical erasing unit to be scanned after all of the plurality of physical programming units in the at least one first physical erasing unit are finished scanning.

11. The memory storage device of claim 8 , wherein the memory control circuit unit is further configured to update a third read count of the first physical unit group according to a total read count of the read operation performed on th

Assignees

• Phison Electronics Corp

Inventors

• Zeng Shih-Jia
• Su Po-Cheng
• Wang Chih-Wei
• Lin Wei

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title