Electronic device with a reference voltage generator circuit and an adaptive cascode circuit

US11797040B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11797040-B2
Application numberUS-202117385010-A
CountryUS
Kind codeB2
Filing dateJul 26, 2021
Priority dateNov 30, 2020
Publication dateOct 24, 2023
Grant dateOct 24, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device including: a reference voltage generator circuit to generate a reference voltage based on a first and second voltage, the reference voltage generator circuit including: a first current source to supply a first current to each of a first and second node; an amplifier to amplify a difference between the first voltage of the first node and the second voltage of the second node and to output a difference voltage corresponding to the amplified difference; a first bipolar junction transistor (BJT) connected to the first node; a first resistor connected to the second node; a second BJT connected between the first resistor and ground; a second resistor connected between the second node and ground; and a first transistor to be supplied with a second current from the first current source; and an adaptive cascode circuit to generate a bias voltage applied to a gate of the first transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device, comprising: a reference voltage generator circuit configured to generate a reference voltage based on a first voltage and a second voltage, the reference voltage generator circuit including: a first current source configured to supply a first current to each of a first node and a second node; an amplifier configured to amplify a difference between the first voltage of the first node and the second voltage of the second node and to output a difference voltage corresponding to the amplified difference; a first bipolar junction transistor (BJT) connected to the first node; a first resistor connected to the second node; a second BJT connected between the first resistor and a ground terminal; a second resistor connected between the second node and the ground terminal; and a first transistor configured to be supplied with a second current from the first current source; and an adaptive cascode circuit configured to generate a bias voltage to be applied to a gate of the first transistor, wherein the adaptive cascode circuit includes: a second transistor including a gate to which the bias voltage is applied and a second terminal to which the bias voltage is applied; and a third transistor including a gate to which the bias voltage is applied. 2. The electronic device of claim 1 , wherein the first current source includes: a first source transistor connected to the first node and to which the first current is supplied; a second source transistor connected to the second node and to which the first current is supplied; and a third source transistor including a gate connected to an output terminal of the amplifier and to which the second current is supplied, wherein a first terminal of the third source transistor is connected to a first terminal of the first transistor. 3. The electronic device of claim 2 , wherein the first voltage, the second voltage, and a third voltage, which is applied to the first terminal of the first transistor, are the same. 4. The electronic device of claim 1 , wherein the adaptive cascode circuit includes: a fourth transistor including a gate connected to an output terminal of the amplifier and configured to receive the difference voltage and to output a third current in response to the difference voltage; and a fifth transistor including a gate connected to the output terminal of the amplifier and configured to receive the difference voltage and to output a fourth current in response to the difference voltage, an amount of the fourth current being the same as an amount of the second current. 5. The electronic device of claim 1 , further comprising: a second current source configured to supply a third current to each of the second transistor and the third transistor, an amount of the third current being the same as an amount of the second current. 6. The electronic device of claim 1 , wherein a voltage applied to the first terminal of the second transistor, a voltage applied to a first terminal of the third transistor, and a voltage applied to a first terminal of the first transistor are the same. 7. The electronic device of claim 1 , wherein the adaptive cascode circuit further includes: a sixth transistor including a first terminal to which the bias voltage is applied and a second terminal connected to the ground terminal; a seventh transistor including a gate connected to a gate of the sixth transistor, a first terminal connected to the gate of the sixth transistor, and a second terminal connected to the ground terminal; and a current source configured to supply a first mirror current to each of the sixth transistor and the seventh transistor, an amount of the first mirror current being the same as an amount of the second current. 8. The electronic device of claim 7 , wherein a size of the sixth transistor is the same as a size of the seventh transistor. 9. The electronic device of claim 1 , wherein the adaptive cascode circuit includes: a second current source; an eighth transistor connected between the second current source and the ground terminal; and a third resistor connected in parallel with the eighth transistor. 10. The electronic device of claim 9 , wherein the second current source supplies a replica current to the eighth transistor, an amount of the replica current being the same as an amount of the first current. 11. The electronic device of claim 9 , wherein the eighth transistor is implemented with a BJT, and wherein an emitter-base voltage of the eighth transistor is the same as the emitter-base voltage of the first BJT. 12. An electronic device, comprising: a reference voltage generator circuit configured to generate a reference voltage based on a first voltage and a second voltage, the reference voltage generator circuit including: a first current source configured to supply a first current to each of a first node and a second node; an amplifier configured to amplify a difference between the first voltage of the first node and the second voltage of the second node; and a first transistor supplied with a second current from the first current source; and an adaptive cascode circuit configured to generate a bias voltage to be applied to a gate of the first transistor; and a start-up circuit configured to supply, to the adaptive cascode circuit, a start-up voltage for adjusting a magnitude of the bias voltage, wherein the first voltage, the second voltage, and a voltage of a first terminal of the first transistor, which is connected to the first current source, are the same. 13. The electronic device of claim 12 , wherein the reference voltage generator circuit further includes: a first bipolar junction transistor (BJT) connected between the first node and a ground terminal, and wherein the adaptive cascode circuit compensates for a change of an emitter-base voltage of the first BJT, which occurs due to a temperature change, by using the bias voltage. 14. The electronic device of claim 12 , wherein the adaptive cascode circuit includes: a second transistor including a first terminal connected to the gate of the first transistor and a gate to which the start-up voltage is applied. 15. The electronic device of claim 14 , wherein the start-up voltage has a magnitude the same as a magnitude of a driving voltage, which is supplied to the electronic device, from when the electronic device is initialized to a first time when a magnitude of the reference voltage corresponds to a first level, and has a magnitude the same as a magnitude of a ground voltage after the first time. 16. The electronic device of claim 12 , wherein the adaptive cascode circuit further includes: a voltage buffer circuit including a second transistor including a gate to which the bias voltage is applied and a second terminal to which the bias voltage is applied, and a third transistor including a gate to which the bias voltage is applied and through which a third current flows, an amount of the third current being the same as an amount of the second current; a first current mirror circuit connected to the voltage buffer circuit and configured to mirror the third current; a second current source circuit configured to supply the third current to the voltage buffer circuit; and a replica circuit including a replica transistor supplied with a replica current from the second current source and to which the first voltage is applied, a magnitude of the replica current being the same as a magnitude of the first current. 17. An electronic device, comprising: a reference voltage generator

Assignees

Inventors

Classifications

  • G05F3/267Primary

    using both bipolar and field-effect technology · CPC title

  • using an operational amplifier as final control device · CPC title

  • characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

  • G05F3/30Primary

    Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

  • G05F1/10Primary

    Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

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What does patent US11797040B2 cover?
An electronic device including: a reference voltage generator circuit to generate a reference voltage based on a first and second voltage, the reference voltage generator circuit including: a first current source to supply a first current to each of a first and second node; an amplifier to amplify a difference between the first voltage of the first node and the second voltage of the second node…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G05F3/267. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 24 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).