Matrix-vector multiplication using sot-based non-volatile memory cells
US-2022044103-A1 · Feb 10, 2022 · US
US11793002B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11793002-B2 |
| Application number | US-202117308499-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 5, 2021 |
| Priority date | May 5, 2021 |
| Publication date | Oct 17, 2023 |
| Grant date | Oct 17, 2023 |
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A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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What is claimed is: 1. A resistive memory device, comprising: a magnetic tunnel junction structure comprising a free magnetic layer, wherein the free magnetic layer comprises a magnetic material which hosts multiple topological spin textures that are induced in response to programming pulses applied to the resistive memory device to tune a conductance state of the resistive memory device. 2. The device of claim 1 , wherein the magnetic tunnel junction structure comprises: a first pinned magnetic layer; and a non-magnetic layer of insulating material disposed between the first pinned magnetic layer and the free magnetic layer; wherein the first pinned magnetic layer and the free magnetic layer comprise a perpendicular magnetic anisotropy. 3. The device of claim 2 , wherein the magnetic tunnel junction structure further comprises a second pinned magnetic layer, wherein the free magnetic layer is disposed between the first and second pinned magnetic layers. 4. The device of claim 3 , wherein the first and second pinned magnetic layers each comprise a footprint area which is smaller than a footprint area of the free magnetic layer. 5. The device of claim 2 , wherein the free magnetic layer comprises a multilayer structure, wherein the multilayer structure comprises a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first and second heavy metal layers. 6. The device of claim 5 , wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises a cobalt-iron-boron alloy, and the second heavy metal layer comprises tantalum. 7. The device of claim 5 , wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises a cobalt-iron-boron alloy, and the second heavy metal layer comprises iridium. 8. The device of claim 5 , wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises iron, and the second heavy metal layer comprises iridium. 9. The device of claim 1 , wherein the free magnetic layer comprises a single non-centrosymmetric chiral magnetic layer. 10. The device of claim 9 , wherein the single non-centrosymmetric chiral magnetic layer comprises one of a cobalt-iron-silicon alloy, and an iron-germanium alloy. 11. The device of claim 1 , wherein the topological spin textures comprise skyrmions. 12. A device, comprising: an array of non-volatile resistive memory cells, wherein at least one non-volatile resistive memory cell comprises a resistive memory device, wherein the resistive memory device comprises a magnetic tunnel junction structure comprising a free magnetic layer, wherein the free magnetic layer comprises a magnetic material which hosts multiple topological spin textures that are induced in response to programming pulses applied to the resistive memory device to tune a conductance state of the resistive memory device. 13. The device of claim 12 , wherein the magnetic tunnel junction structure of the resistive memory device comprises: a pinned magnetic layer; and a non-magnetic layer of insulating material disposed between the pinned magnetic layer and the free magnetic layer; wherein the pinned magnetic layer and the free magnetic layer comprise a perpendicular magnetic anisotropy. 14. The device of claim 12 , wherein the free magnetic layer comprises a multilayer structure, wherein the multilayer structure comprises a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first and second heavy metal layers. 15. The device of claim 12 , wherein the free magnetic layer comprises a single non-centrosymmetric chiral magnetic layer. 16. The device of claim 12 , wherein the device comprises a neuromorphic computing device, wherein the array of non-volatile resistive memory cells comprises an array of artificial synaptic elements, wherein the at least one non-volatile resistive memory cell comprises a synaptic weight encodable by a conductance value of the resistive memory device of the at least one non-volatile memory cell. 17. The device of claim 12 , wherein the topological spin textures comprise skyrmions. 18. A method, comprising applying one or more programming pulses to a resistive memory device comprising a free magnetic layer responsive to the programming pulses to configure one or more topological spin textures in the free magnetic layer to tune the conductance state of the resistive memory device. 19. The method of claim 18 , wherein applying one or more programming pulses to the resistive memory device configure one or more topological spin textures in the free magnetic layer to tune the conductance state of the resistive memory device comprises: applying one or more potentiation programming pulses to induce a formation of one or more topological spin textures in the free magnetic layer as a result of current flow in a first direction through the resistive memory device; and applying one or more depression programming pulses to cause annihilation of one or more existing topological spin textures in the free magnetic layer as a result of current flow in a second direction through the resistive memory device, opposite the first direction. 20. The method of claim 18 , wherein the topological spin textures comprise magnetic skyrmions, and wherein the free magnetic layer comprises a chiral magnetic layer.
Materials of the active region · CPC title
comprising selection components having three or more electrodes, e.g. transistors · CPC title
Reading or sensing circuits or methods · CPC title
Writing or programming circuits or methods · CPC title
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