Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11792976-B2
Application number	US-202117371558-A
Country	US
Kind code	B2
Filing date	Jul 9, 2021
Priority date	Dec 10, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate including a memory cell region, an active region in the memory cell region, a peripheral region, and a logic active region in the peripheral region;
an element isolation structure between the active region and the logic active region, the element isolation structure defining the active region and the logic active region;
an insulating layer pattern covering the active region, the insulating layer pattern including an extension portion that extends along the element isolation structure, is spaced apart from the element isolation structure, and overhangs over the element isolation structure, and the insulating layer pattern including a stacked structure in which a second insulating layer pattern having a second extension portion is on a first insulating layer pattern having a first extension portion; and
a support insulating layer filling a recess space defined between the extension portion and the element isolation structure, wherein
a portion of the element isolation structure bordering the support insulating layer has a non-flat surface, wherein
an extension length of the second extension portion is greater than an extension length of the first extension portion.

2. The semiconductor memory device of claim 1 , wherein the support insulating layer includes silicon oxide implanted with nitrogen ions.

3. The semiconductor memory device of claim 1 , wherein a thickness of the second insulating layer pattern is greater than a thickness of the first insulating layer pattern.

4. The semiconductor memory device of claim 1 , further comprising:
a mask insulating pattern between the first extension portion and the element isolation structure, wherein
the support insulating layer fills the recess space defined between the element isolation structure and a portion of the second extension portion further extending from the first extension portion over the element isolation structure, and
the mask insulating pattern includes a material having a different impurity type or impurity concentration than an impurity or impurity concentration included in the support insulating layer.

5. The semiconductor memory device of claim 1 , further comprising:
a transistor including a gate insulating layer and a gate line on the logic active region, wherein
a material in the support insulating layer is the same as a material in at least a portion of the gate insulating layer.

6. The semiconductor memory device of claim 5 , wherein
the gate insulating layer has a stacked structure in which a second gate insulating layer pattern is on a first gate insulating layer pattern,
the first gate insulating layer pattern has a first thickness,
the second gate insulating layer pattern has a second thickness,
the second thickness is less than the first thickness, and
a material in the support insulating layer is the same as a material in the first gate insulating layer pattern.

7. The semiconductor memory device of claim 6 , wherein a permittivity of the second gate insulating layer pattern is higher than a permittivity of the first gate insulating layer pattern.

8. The semiconductor memory device of claim 6 , wherein
the support insulating layer has a third thickness,
the third thickness is at least twice or greater than the first thickness of the first gate insulating layer pattern.

9. A semiconductor memory device comprising:
a substrate including a memory cell region, an active region in the memory cell region, a peripheral region, and a logic active region in the peripheral region;
an element isolation structure between the active region and the logic active region, the element isolation structure defining the active region and the logic active region;
an insulating layer pattern covering the active region, the insulating layer pattern having a stacked structure in which a second insulating layer pattern is on a first insulating layer pattern extending over the element isolation structure between the active region and the logic active region; and
a support insulating layer between the insulating layer pattern and the element isolation structure, wherein
the first insulating layer pattern includes a first extension portion,
the second insulating layer pattern includes a second extension portion, an extension length of the second extension portion is greater than an extension length of the first extension portion,
each of the first extension portion and the second extension portion extend along the element isolation structure, are spaced apart from the element isolation structure, and overhang over the element isolation structure, and
the support insulating layer fills a recess space defined between the element isolation structure and a portion of the second extension portion extends over the element isolation structure from the first extension portion.

10. The semiconductor memory device of claim 9 , further comprising:
a first transistor on the logic active region,
the first transistor including a gate insulating layer having a stacked structure and a gate line on the gate insulating layer, the stacked structure including a second gate insulating layer pattern on a first gate insulating layer pattern, the second gate insulating layer pattern having a second thickness and a second permittivity, the first gate insulating layer pattern having a first thickness and a first permittivity, the second thickness being less than the first thickness, and the second permittivity of the second gate insulating layer pattern being greater than first permittivity of the first gate insulating layer pattern, wherein
a material included in the support insulating layer is the same as a material included in the first gate insulating layer pattern.

11. The semiconductor memory device of claim 10 , wherein the support insulating layer has a third thickness that is at least twice as large as the first thickness of the first gate insulating layer pattern.

12. The semiconductor memory device of claim 10 , further comprising:
a second transistor on the logic active region, wherein
the second transistor includes the second gate insulating layer pattern and a gate line on the second gate insulating layer pattern.

13. The semiconductor memory device of claim 9 , wherein the support insulating layer includes silicon oxide implanted with nitrogen ions.

14. The semiconductor memory device of claim 9 , further comprising:
a mask insulating pattern between the first extension portion and the element isolation structure, wherein
the mask insulating pattern is closer to the active region than the support insulating layer, and
the mask insulating pattern includes silicon oxide having a different impurity type or impurity concentration than an impurity type or impurity concentration in the support insulating layer.

15. The semiconductor memory device of claim 9 , further comprising:
a gate dielectric layer, a word line, and a buried insulating layer sequentially disposed in a word line trench extending across the active region in the memory cell region, wherein
the insulating layer pattern covers the active region and the buried insulating layer together.

16. A semiconductor memory device comprising:
a substrate including a memory cell region, a plurality of active regions in the memory cell region, a peripheral region, and a plurality of logic active regions in the peripheral region, the substrate defining a plurality of word line trenches extending in parallel with each other in a horizontal direction across the plurality of active regions in t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dongoh
• Kil Gyuhyun
• HAN Junghoon
• Back Doosan

Classifications

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/053 Primary

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title