Solid-state imaging device and method of controlling solid-state imaging device

US11792541B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11792541-B2
Application numberUS-202217901994-A
CountryUS
Kind codeB2
Filing dateSep 2, 2022
Priority dateAug 31, 2017
Publication dateOct 17, 2023
Grant dateOct 17, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solid-state imaging device according to an embodiment of the disclosure includes a first electrode, a second electrode, a photoelectric conversion layer, and a voltage applier. The first electrode includes a plurality of electrodes independent from each other. The second electrode is disposed opposite to the first electrode. The photoelectric conversion layer is disposed between the first electrode and the second electrode. The voltage applier applies different voltages to at least one of the first electrode or the second electrode during a charge accumulation period and a charge non-accumulation period.

First claim

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The invention claimed is: 1. A solid-state imaging device, comprising: a first electrode including a plurality of electrodes, wherein the plurality of electrodes includes a charge readout electrode and an accumulation electrode; a second electrode opposite to the first electrode; a photoelectric conversion layer between the first electrode and the second electrode; and a voltage applier configured to apply different voltages during a charge accumulation period and a charge non-accumulation period to at least one of the first electrode or the second electrode. 2. The solid-state imaging device according to claim 1 , wherein the first electrode further includes a discharge electrode. 3. The solid-state imaging device according to claim 1 , wherein the first electrode further includes a first barrier adjustment electrode between the charge readout electrode and the accumulation electrode, and the first barrier adjustment electrode is configured to adjust a voltage across the charge readout electrode and the accumulation electrode. 4. The solid-state imaging device according to claim 1 , wherein the first electrode further includes a second barrier adjustment electrode on a side of the charge readout electrode opposite to the accumulation electrode, and the second barrier adjustment electrode is configured to adjust a voltage across the charge readout electrode and the accumulation electrode. 5. The solid-state imaging device according to claim 1 , wherein a voltage across the charge readout electrode and the accumulation electrode is larger during the charge non-accumulation period than during the charge accumulation period. 6. The solid-state imaging device according to claim 1 , wherein a potential difference between the accumulation electrode and the second electrode is larger during the charge non-accumulation period than during the charge accumulation period. 7. The solid-state imaging device according to claim 2 , wherein the charge readout electrode also serves as the discharge electrode. 8. The solid-state imaging device according to claim 1 , wherein the accumulation electrode is divided into a plurality of segments, and each segment of the plurality of segments is configured to receive a different voltage. 9. The solid-state imaging device according to claim 2 , further comprising an insulating layer between the first electrode and the photoelectric conversion layer, wherein the charge readout electrode and the discharge electrode are electrically coupled with the photoelectric conversion layer via an opening in the insulating layer. 10. The solid-state imaging device according to claim 9 , further comprising a semiconductor layer between the photoelectric conversion layer and the insulating layer, wherein the charge readout electrode is electrically coupled with the photoelectric conversion layer via the semiconductor layer. 11. The solid-state imaging device according to claim 1 , wherein each of the plurality of electrodes is configured to receive a separate voltage. 12. The solid-state imaging device according to claim 1 , further comprising: an organic photoelectric transducer; and an inorganic photoelectric transducer, wherein the organic photoelectric transducer is on the inorganic photoelectric transducer, the organic photoelectric transducer includes at least one photoelectric conversion layer, and the inorganic photoelectric transducer is configured to perform photoelectric conversion in a different wavelength band from the organic photoelectric transducer. 13. The solid-state imaging device according to claim 12 , wherein, the inorganic photoelectric transducer is in a semiconductor substrate, and the organic photoelectric transducer is on a first surface side of the semiconductor substrate. 14. The solid-state imaging device according to claim 13 , wherein a multilayer wiring layer is on a second surface side of the semiconductor substrate. 15. A method of controlling a solid-state imaging device, comprising: applying different voltages to at least one of a first electrode or a second electrode during a charge accumulation period and a charge non-accumulation period, wherein the first electrode includes a plurality of electrodes, the plurality of electrodes includes a charge readout electrode and an accumulation electrode, the second electrode is opposite to the first electrode, and a photoelectric conversion layer is between the first electrode and the second electrode. 16. The method of controlling the solid-state imaging device according to claim 15 , wherein the first electrode further includes a first barrier adjustment electrode between the charge readout electrode and the accumulation electrode, and a voltage is applied to the first barrier adjustment electrode during the charge non-accumulation period to cause a voltage across the charge readout electrode and the accumulation electrode to be larger during the charge non-accumulation period than during the charge accumulation period. 17. The method of controlling the solid-state imaging device according to claim 15 , wherein a reset voltage applied at a shutter timing after the charge accumulation period is larger than the reset voltage applied at a shutter timing before the charge accumulation period. 18. The method of controlling the solid-state imaging device according to claim 15 , wherein a voltage is applied to the second electrode during the charge non-accumulation period, and a potential difference between the accumulation electrode and the second electrode is larger during the charge non-accumulation period than during the charge accumulation period. 19. The method of controlling the solid-state imaging device according to claim 15 , wherein charges accumulated on the accumulation electrode are discharged from the charge readout electrode in several batches during the charge non-accumulation period. 20. The method of controlling the solid-state imaging device according to claim 15 , wherein a gate of a reset transistor is always turned on during the charge non-accumulation period.

Assignees

Inventors

Classifications

  • Image sensors · CPC title

  • H10F39/813Primary

    Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

  • Colour separation based on photon absorption depth, e.g. full colour resolution obtained simultaneously at each pixel location · CPC title

  • H04N25/626Primary

    Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

  • Organic image sensors · CPC title

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What does patent US11792541B2 cover?
A solid-state imaging device according to an embodiment of the disclosure includes a first electrode, a second electrode, a photoelectric conversion layer, and a voltage applier. The first electrode includes a plurality of electrodes independent from each other. The second electrode is disposed opposite to the first electrode. The photoelectric conversion layer is disposed between the first ele…
Who is the assignee on this patent?
Sony Semiconductor Solutions Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/813. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 17 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).