Wide bandgap transistors with gate-source field plates

Patent metadata

Field	Value
Publication number	US-11791385-B2
Application number	US-7826505-A
Country	US
Kind code	B2
Filing date	Mar 11, 2005
Priority date	Mar 11, 2005
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A spacer layer is on at least part of the surface of the plurality of active region between the gate and the drain electrode and between the gate and the source electrode. A field plate is on the spacer layer and extends on the spacer and over the active region toward the drain electrode. The field plate also extends on the spacer layer over the active region and toward the source electrode. At least one conductive path electrically connects the field plate to the source electrode or the gate.

First claim

We claim:

1. A transistor, comprising:
an active region comprising a channel layer, said channel layer comprising a two dimensional electron gas (2DEG) region;
a source electrode and a drain electrode in electrical contact with said active region;
a metal gate between said source electrode and said drain electrode and on said active region;
a metal first field plate that is integral with said gate;
a first spacer layer on said active region between said gate and said drain electrode and between said gate and said source electrode,
wherein said first field plate extends on said first spacer layer over a vertical projection of said active region from a first vertical edge of said gate toward said drain electrode and from a second vertical edge of said gate toward said source electrode, and wherein said second vertical edge is opposite from said first vertical edge;
a second spacer layer;
a second field plate on said second spacer layer, said second spacer layer separating said second field plate from said gate and from said first field plate; and
a conductive path electrically connecting said second field plate to said source electrode, wherein in a plan view said conductive path comprises a first portion that extends from the second field plate to beyond the vertical projection of the active region, and a second portion that extends from beyond the vertical projection of the active region to the source electrode, and wherein the second field plate and the source electrode are on the active region.

2. The transistor of claim 1 , wherein said first field plate extends on said first spacer layer a first lateral distance L fd from said first vertical edge of said gate toward said drain electrode, wherein said first field plate extends on said first spacer layer a second lateral distance L fs from said second vertical edge of said gate toward said source electrode, and wherein said first lateral distance L fd is greater than said second lateral distance L fs .

3. The transistor of claim 1 , wherein said second spacer layer covers said gate and said second field plate overlaps said gate and extends on said second spacer layer past said first vertical edge of said gate toward said drain electrode and extends on said second spacer layer past said second vertical edge of said gate toward said source electrode.

4. The transistor of claim 1 , wherein said active region is on a substrate.

5. The transistor of claim 1 , wherein said active region comprises Group-III nitride based semiconductor materials.

6. The transistor of claim 1 , wherein said first or second spacer layer comprises a dielectric material, or multiple layers of dielectric material.

7. The transistor of claim 1 , wherein said first or second field plate is configured to provide a reduction in peak operating electric field on a drain side of said gate and a source side of said gate.

8. The transistor of claim 7 , wherein said reduction in peak operating electric field increases a breakdown voltage of said transistor.

9. The transistor of claim 7 , wherein said reduction in peak operating electric field reduces trapping.

10. The transistor of claim 7 , wherein said reduction in peak operating electric field reduces leakage currents in said transistor.

11. The transistor of claim 1 , comprising a high electron mobility transistor (HEMT).

12. The transistor of claim 1 , further comprising one or more additional spacer layer and field plate pairs, each spacer layer in said pairs providing physical separation between sequential field plates, each field plate in said pairs electrically connected to said source electrode or said gate.

13. The transistor of claim 1 , wherein said first field plate comprises separate source and drain field plates, said source field plate extending on said first spacer layer toward said source electrode and said drain field plate extending on said first spacer layer toward said drain electrode, said source and drain field plates electrically connected to said source electrode or said gate.

14. The transistor of claim 1 , wherein said first field plate comprises separate source and drain field plates, said source field plate extending on said first spacer layer toward said source electrode and said drain field plate extending on said first spacer layer toward said drain electrode, said source field plate electrically connected to one of said source electrode and said gate, said drain field plate connected to the other of said source electrode and said gate.

15. The transistor of claim 1 , wherein an entirety of a conduction channel between the source electrode and the drain electrode is free of vertical overlap with the first portion and the second portion of said conductive path.

16. The transistor of claim 1 , wherein the first portion extends away from the second field plate in a first direction, and the second portion extends toward the source electrode in a second direction that is different from the first direction.

17. The transistor of claim 16 , wherein the second direction is opposite to the first direction.

18. The transistor of claim 17 , further comprising a connecting portion that extends from the first portion to the second portion in a third direction that is different from the first and second directions.

19. A transistor, comprising:
a buffer layer and barrier layer successively on a substrate;
an active region comprising a two dimensional electron gas (2DEG) channel layer at a heterointerface between said buffer layer and said barrier layer;
a source electrode and a drain electrode both making electrical contact with said 2DEG channel layer;
a metal gate on said barrier layer between said source electrode and said drain electrode, the gate comprising a metal first field plate that is integral with the gate;
a first spacer layer on said barrier layer between said gate and said drain electrode and between said gate and said source electrode,
wherein the first field plate is on said first spacer layer, said first field plate comprising a first portion extending on said first spacer layer over said barrier layer a first distance from a first vertical edge of said gate toward said drain electrode and a second portion extending on said first spacer layer over said barrier layer a second distance from a second vertical edge of said gate toward said source electrode, wherein said second vertical edge is opposite from said first vertical edge, and wherein said first spacer layer separates said first field plate from said barrier layer;
a second spacer layer and a second field plate on said second spacer layer, with said second field plate over less than all of said first field plate and with said second spacer layer separating said second field plate from said first field plate; and
a conductive path electrically connecting said second field plate to said source electrode, wherein in a plan view at least a portion of said conductive path extending from the second field plate to beyond a vertical projection of said active region, and from beyond the vertical projection of said active region to the source electrode, and wherein the second field plate and the source electrode are on said active region.

20. The transistor of claim 19 , wherein said first distance is greater than said second distance.

21. The transistor of claim 19 , wherein said first distance is in a range of 0.2 to 5 microns and said second distance is in a range of 0.1 to 2 microns.

22. A transistor, comprising:
a

Assignees

• Wu Yifeng
• Parikh Primit
• Mishra Umesh
• Sheppard Scott
• Wolfspeed Inc

Inventors

• Wu Yifeng
• Parikh Primit
• Mishra Umesh
• Sheppard Scott

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D64/111 Primary

  Field plates · CPC title

• H01L29/402 Primary

  Electricity · mapped topic