Memory device performing read operation and operating method of the memory device

Patent metadata

Field	Value
Publication number	US-11790979-B2
Application number	US-202117364137-A
Country	US
Kind code	B2
Filing date	Jun 30, 2021
Priority date	Dec 28, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.

First claim

What is claimed is:

1. A memory device, comprising:
a memory block coupled to a plurality of local word lines;
a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines through a pass switch circuit and configured to perform a read operation on the memory block; and
control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit, and discharge potential levels of the plurality of local word lines using the leakage current of the pass switch circuit when the memory device enters a ready state after the read operation,
wherein the leakage current of the pass switch circuit is caused or increased by applying a positive voltage to, or floating body regions of a plurality of pass transistors in the pass switch circuit.

2. The memory device of claim 1 ,
wherein the pass switch circuit includes the plurality of pass transistors coupling the plurality of local word lines to the plurality of global word lines, respectively, and precharges the body regions of the plurality of pass transistors to the positive voltage, or floats the body regions of the plurality of pass transistors to cause or increase the leakage current.

3. The memory device of claim 2 ,
wherein the control logic controls the peripheral circuit to perform the read operation including a read voltage applying operation and a word line discharge operation,
wherein the read voltage applying operation comprises applying a read voltage to a selected local word line, among the plurality of local word lines, and applying a pass voltage to unselected local word lines, among the plurality of local word lines, and
wherein the word line discharge operation comprises applying a ground voltage to the plurality of local word lines.

4. The memory device of claim 3 ,
wherein the memory device is in a busy state when the read operation is being performed, and the memory device is in the ready state when the read operation is completed.

5. The memory device of claim 4 ,
wherein when the memory device enters the ready state, the pass switch circuit applies a block selection signal having a low level to gates of the plurality of pass transistors, and applies the positive voltage to, or floats the body regions of the plurality of pass transistors.

6. The memory device of claim 3 ,
wherein the peripheral circuit discharges the potential levels of the plurality of local word lines boosted to the positive voltage to a ground voltage level as a channel potential of the memory block boosted to a negative voltage is recovered to the ground voltage level.

7. The memory device of claim 6 ,
wherein the potential levels of the plurality of local word lines are discharged to the ground voltage level as the leakage current of the plurality of pass transistors is caused or increased.

8. The memory device of claim 7 ,
wherein each of the plurality of local word lines is coupled to a drain terminal of each of the plurality of pass transistors, and
wherein each of the plurality of global word lines is coupled to at least two source terminals of the plurality of pass transistors.

9. The memory device of claim 2 ,
wherein each of the plurality of pass transistors is a negative metal-oxide semiconductor (NMOS) transistor or a positive metal-oxide semiconductor (PMOS) transistor.

10. A method of operating a memory device, the method comprising:
performing a read operation on a memory block coupled to a plurality of local word lines; and
causing or increasing a leakage current of a pass switch circuit coupling the plurality of local word lines to a plurality of global word lines by applying a positive voltage to, or floating body regions of a plurality of pass transistors in the pass switch circuit; and
discharging potential levels of the plurality of local word lines using the leakage current of the pass switch circuit when the memory device enters a ready state.

11. The method of claim 10 , wherein the performing of the read operation comprises:
performing a read voltage applying operation of applying a read voltage to a selected local word line, among the plurality of local word lines, and applying a pass voltage to unselected local word lines, among the plurality of local word lines; and
performing a word line discharge operation of applying a ground voltage to the plurality of local word lines.

12. The method of claim 11 ,
wherein the pass switch circuit includes the plurality of pass transistors coupling the plurality of local word lines to the plurality of global word lines, respectively.

13. The method of claim 12 ,
wherein the causing or increasing of the leakage current comprises precharging the body regions of the plurality of pass transistors to the positive voltage, or floating the body regions of the plurality of pass transistors.

14. The method of claim 13 , further comprising setting the memory device to a busy state when the read operation is being performed, and setting the memory device to the ready state when the read operation is completed.

15. The method of claim 14 , wherein the causing or increasing of the leakage current comprises:
applying a block selection signal having a low level to gates of the plurality of pass transistors when the memory device enters the ready state; and
applying the positive voltage to the body regions of the plurality of pass transistors, or floating the body regions of the plurality of pass transistors.

16. The method of claim 12 , wherein the discharging of the potential levels of the plurality of local word lines comprises discharging the potential levels of the plurality of local word lines boosted to the positive voltage to a ground voltage level when a channel potential of the memory block boosted to a negative voltage by the word discharge operation is recovered to the ground voltage level.

17. The method of claim 16 ,
wherein the potential levels of the plurality of local word lines are discharged to the ground voltage level as the leakage current of the plurality of pass transistors is caused or increased.

18. The method of claim 17 ,
wherein each of the plurality of local word lines is coupled to a drain terminal of each of the plurality of pass transistors, and each of the plurality of global word lines is coupled to at least two source terminals of the plurality of pass transistors.

19. The method of claim 12 ,
wherein each of the plurality of pass transistors is a negative metal-oxide semiconductor (NMOS) transistor or a positive metal-oxide semiconductor (PMOS) transistor.

Assignees

• Sk Hynix Inc

Inventors

• Choi Gil Bok
• Yun dae hwan

Classifications

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title