Sensitivity amplifier

Patent metadata

Field	Value
Publication number	US-11790959-B2
Application number	US-202017430709-A
Country	US
Kind code	B2
Filing date	Jun 19, 2020
Priority date	Nov 28, 2019
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

The disclosure provides a sense amplifier and a control method thereof. The sense amplifier includes: a pre-charge module, a first input and output terminal, a second input and output terminal, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit. The sense amplifier can compensate for the offset voltage. The result is a sense amplifier with greatly reduced offset voltage, thereby improving the sensitivity and resolution of the sense amplifier.

First claim

What is claimed is:

1. A sensitivity amplifier, comprising:
a pre-charge module;
a first input and output terminal, a second input and output terminal, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit, and a second energy storage unit;
wherein a first end of the pre-charge module is connected to a first bit line, and a second end of the pre-charge module is connected to a second bit line, and wherein the pre-charge module pre-charges the first bit line and the second bit line to a preset voltage;
wherein the first input and output terminal is connected to the first bit line and the second input and output terminal is connected to the second bit line;
wherein a gate of the first PMOS transistor is connected to the second input and output terminal via the second switch unit, and a drain of the first PMOS transistor is connected to the first input and output terminal via the first switch unit; a gate of the second PMOS transistor is connected to the first input and output terminal through the first switch unit; and a drain of the second PMOS transistor is connected to the second input and output terminal through the second switch unit; wherein a gate of the first NMOS transistor is connected to the second input and output terminal, and is further connected to the first input and output terminal via the third switch unit, a drain of the first NMOS transistor is connected to the first input and output terminal through the third switch unit; wherein a gate of the second NMOS transistor is connected to the first input and output terminal and is further connected is connected to the second input and output terminal through the fourth switch unit, and a drain of the second NMOS transistor is connected to the second input and output terminal via the fourth switch unit;
wherein a first end of the fifth switch unit is connected to a power supply voltage, and a second end of the fifth switch unit is connected to the first input and output terminal;
wherein a first end of the sixth switch unit is connected to the power supply voltage, and the other end of the sixth switch unit is connected to the second input and output terminal;
wherein a first end of the first energy storage unit is connected to the first input and output terminal, and a second end of the first energy storage unit is grounded via the seventh switch unit;
wherein a first end of the second energy storage unit is connected to the second input and output terminal, and a second end of the second energy storage unit is grounded via the eighth switch unit; and
wherein the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit configure the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor in an amplification mode or a diode mode.

2. The sensitivity amplifier according to claim 1 , further comprising: a ninth switch unit and a tenth switch unit, wherein a first end of the ninth switch unit is connected to the first bit line, a second end of the ninth switch unit is connected to the second end of the first energy storage unit; wherein a first end of the tenth switch unit is connected to the second bit line, and a second end of the tenth switch unit is connected to the second end of the second energy storage unit.

3. The sensitivity amplifier according to claim 1 , wherein the sensitivity amplifier further comprises: an eleventh switch unit and a twelfth switch unit, wherein a first end of the eleventh switch unit is connected to the first bit line, a second end of the eleventh switch unit is connected to the first input and output terminal; wherein a first end of the twelfth switch unit is connected to the second bit line, and a second end of the twelfth switch unit is connected to the second input and output terminal.

4. The sensitivity amplifier according to claim 1 , further comprising: a first driving transistor and a second driving transistor, wherein a first end of the first driving transistor is connected to the power supply voltage, and a second end of the first driving transistor is connected to a source of the first PMOS transistor and a source of the second PMOS transistor; wherein a first end of the second drive transistor is grounded, and a second end of the second drive transistor is connected to a source of the first NMOS transistor and a source of the second NMOS transistor.

5. The sensitivity amplifier of claim 4 , wherein the first driving transistor comprises a PMOS transistor, a source of the first driving transistor is connected to the power supply voltage, and a drain of the first driving transistor is connected to the source of the first PMOS transistor and the source of the second PMOS transistor; wherein the second driving transistor comprises an NMOS transistor, a source of the second driving transistor is grounded, and a drain of the second driving transistor is connected with the source of the first NMOS transistor and the source of the second NMOS transistor.

6. The sensitivity amplifier of claim 1 , further comprising:
a first switch transistor, a second switch transistor, a third energy storage unit, and a fourth energy storage unit;
wherein a first end of the first switch transistor is connected to the first bit line, a second end of the first switch transistor is connected to a first end of the third energy storage unit and a second end of the third energy storage unit is grounded; wherein a first end of the second switch transistor is connected to the second bit line, and a second end of the second switch transistor is connected to a first end of the fourth energy storage unit, and a second end of the fourth energy storage unit is grounded.

7. The sensitivity amplifier of claim 6 , wherein:
the third switch unit comprises a third switch transistor and a fifth switch transistor, and the fourth switch unit comprises a fourth switch transistor and a sixth switch transistor;
one end of the third switch transistor is connected to the first input and output terminal, the other end of the third switch transistor is connected to the drain of the first NMOS transistor; and wherein a first end of the fifth switch transistor is connected to the drain of the first NMOS transistor, and a second end of the fifth switch transistor is connected to a gate of the first NMOS transistor;
a first end of the fourth switch transistor is connected to the second input and output terminal, a second end of the fourth switch transistor is connected to the drain of the second NMOS transistor; and
a first end of the sixth switch transistor is connected to the drain of the second NMOS transistor, and a second end of the sixth switch transistor is connected to the gate of the second NMOS transistor.

8. The sensitivity amplifier of claim 7 , wherein the third switch transistor, the fourth switch transistor, the fifth switch transistor, and the sixth switch transistor are either NMOS transistors or transmission gates composed of NMOS transistors and PMOS transistors.

9. A control method of the sensitivity amplifier as in claim 1 , comprising a plurality of stages:
a pre-charging stage comprising:
pre-charging the first bit line and the second bit line to the preset voltage; and

an offset-voltage compensation stage comprising:
adjusting a connection mode of the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the second NMOS transistor to compensate an offset voltage difference between the first input and

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• G11C7/062 Primary

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title