Semiconductor device

Patent metadata

Field	Value
Publication number	US-11790146-B2
Application number	US-202117324829-A
Country	US
Kind code	B2
Filing date	May 19, 2021
Priority date	Sep 24, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A semiconductor device including a standard cell is provided. The standard cell includes an active region; a gate structure intersecting the active region; a first conductive structure including: a first power supply line and a second power supply line; and a second conductive structure disposed on the first conductive structure, the second conductive structure including: first power distribution patterns spaced apart from each other a first boundary and electrically connected to the first power supply line, second power distribution patterns spaced apart from each other along a second boundary and electrically connected to the second power supply line, net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines, and pin metal lines electrically connected to a second portion of the signal lines.

First claim

What is claimed is:

1. A semiconductor device comprising:
a standard cell comprising:
an active region extending in a first direction on a substrate;
a gate structure intersecting the active region and extending in a second direction intersecting the first direction;
a first conductive structure comprising:
a first power supply line and a second power supply line disposed on the active region and the gate structure and extending in the first direction; and
signal lines disposed between the first power supply line and the second power supply line; and

a second conductive structure disposed on the first conductive structure, the second conductive structure comprising:
first power distribution patterns spaced apart from each other in the first direction along a first boundary of the standard cell and electrically connected to the first power supply line;
second power distribution patterns spaced apart from each other in the first direction along a second boundary of the standard cell and electrically connected to the second power supply line;
net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines; and
pin metal lines electrically connected to a second portion of the signal lines, and extending in the second direction,

wherein the first boundary corresponds to the first power supply line and the second boundary corresponds to the second power supply line,
wherein each of the net metal lines has a center disposed on a central axis extending in the first direction between the first boundary and the second boundary,
wherein, along the second direction, a first distance between the central axis and the first power supply line is substantially equal to a second distance between the central axis and the second power supply line, and
wherein at least one of the pin metal lines is disposed closer to the first boundary or the second boundary than the net metal lines.

2. The semiconductor device of claim 1 , wherein the pin metal lines are asymmetrically disposed with respect to the central axis of the standard cell in the second direction, and
wherein the net metal lines are symmetrically disposed with respect to the central axis of the standard cell in the second direction.

3. The semiconductor device of claim 1 , wherein each of the net metal lines is disposed between a single first power distribution pattern of the first power distribution patterns and a single second power distribution pattern of the second power distribution patterns in the second direction.

4. The semiconductor device of claim 3 , wherein the first power distribution patterns and the second power distribution patterns do not overlap the first boundary and the second boundary adjacent to the pin metal lines.

5. The semiconductor device of claim 1 , wherein a criteria distance d_c corresponds to a sum of a first value corresponding to half of a length of one of the first power distribution patterns in the second direction, and a second value corresponding to a critical spacing distance between end portions of adjacent interconnections, and
wherein the pin metal lines are separated from the first boundary and the second boundary in the second direction by at least a first spacing distance d 1 , and
wherein the first spacing distance d 1 is greater than or equal to zero and the first spacing distance d 1 is less than the criteria distance d_c.

6. The semiconductor device of claim 5 , wherein the net metal lines are separated from the first boundary and the second boundary in the second direction by at least a second spacing distance d 2 , and
wherein the second spacing distance d 2 is greater than or equal to the criteria distance d_c.

7. The semiconductor device of claim 1 , wherein the pin metal lines are interconnection lines of a routing structure between the standard cell and another standard cell that is adjacent to the standard cell.

8. The semiconductor device of claim 7 , wherein at least one of the pin metal lines extends past the first boundary or the second boundary.

9. The semiconductor device of claim 7 , wherein at least one of the pin metal lines is electrically connected to the other standard cell by upper interconnections.

10. The semiconductor device of claim 1 , wherein at least two net metal lines are disposed between a single first power distribution pattern of the first power distribution patterns and a single second power distribution pattern of the second power distribution patterns, and the single first power distribution pattern and the single second power distribution pattern have side surfaces facing each other.

11. The semiconductor device of claim 10 , wherein one of the first power distribution patterns has a first width in the first direction and one of the second power distribution patterns has a second width in the first direction, and
wherein each of the first width and the second width is smaller than a width of the single first power distribution pattern in the first direction.

12. The semiconductor device of claim 1 , wherein the standard cell further comprises:
a contact structure disposed on the active region;
a metal connection structure disposed on the contact structure;
lower power vias disposed on the metal connection structure and electrically connecting the active region to the first power supply line and the second power supply line;
a gate contact structure disposed on the gate structure;
lower connection vias disposed on the gate contact structure and electrically connecting the gate structure to the signal lines;
first power vias disposed on the first power supply line and the second power supply line, and electrically connecting the first power supply line to the first power distribution patterns and the second power supply line to the second power distribution patterns; and
first connection vias disposed on the signal lines and electrically connecting the signal lines to the net metal lines.

13. The semiconductor device of claim 1 , further comprising:
third metal lines disposed on the net metal lines and extending in the first direction; and
second vias disposed between the net metal lines and the third metal lines and electrically connecting the net metal lines to the third metal lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaeha
• Kim Jintae
• Yang Seunghyun
• Heo Dongyeon

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title