Selective reading of memory with improved accuracy

Patent metadata

Field	Value
Publication number	US-11789796-B2
Application number	US-202217843237-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Mar 14, 2013
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.

First claim

The invention claimed is:

1. A memory array comprising:
one or more memory cells to store data and corresponding error correction codes;
an error correction component configured to identify errors in codewords and to correct the errors in the codewords;
a first circuit configured to generate a reference signal;
a second circuit configured to generate a self-reference signal; and
a sense output circuit configured to:
perform a first comparison of the reference signal and a first value read from a selected memory cell of the memory array, the first value read being associated with a first read operation;
detect an error condition associated with the first comparison; and
perform, after the first comparison and based at least in part on the error condition, a second comparison of the self-reference signal and a second value read from the selected memory cell of the memory array, the second value read being associated with a second read operation.

2. The memory array of claim 1 , wherein the error condition indicates an error in the first value read from the selected memory cell as being uncorrectable via the error correction codes.

3. The memory array of claim 1 , wherein the error condition indicates a number of errors in the first value read from the selected memory cell associated with the first comparison including a threshold number of errors greater than 1.

4. The memory array of claim 1 , wherein the error correction component comprises an encoder, or a decoder, or any combination thereof, the error correction component being configured to correct one or more errors in the first value read from the selected memory cell via the error correction codes when the error condition is not detected.

5. The memory array of claim 1 , wherein the sense output circuit comprises:
a multiplexer operatively coupled with the first circuit and the second circuit; and
a sense amplifier.

6. The memory array of claim 5 , wherein the multiplexer is configured to provide the first value read from the selected memory cell or the second value read from the selected memory cell to the sense amplifier.

7. The memory array of claim 5 , wherein the sense amplifier is configured to determine a data digit based at least in part on the first comparison or the second comparison.

8. The memory array of claim 1 , wherein the sense output circuit comprises:
a first sense amplifier associated with a first read type; and
a second sense amplifier associated with a second read type different from the first read type.

9. The memory array of claim 1 , wherein the sense output circuit comprises:
a first sense amplifier associated with a first read type; and
a second sense amplifier associated with a second read type different from the first read type.

10. The memory array of claim 9 , wherein the first sense amplifier is associated with a standard reference read.

11. The memory array of claim 9 , wherein the second sense amplifier is associated with a self-reference read.

12. The memory array of claim 1 , wherein the sense output circuit is further configured to:
output a data digit based on a select signal and at least one of the first comparison or the second comparison.

13. The memory array of claim 12 , wherein the data digit represents data stored in that selected memory cell.

14. The memory array of claim 1 , wherein the sense output circuit is configured to:
operate in a first mode during the performed first comparison.

15. The memory array of claim 14 , wherein the sense output circuit is configured to:
activate a second mode different from a first mode based at least in part on the error condition indicating an error in the first value read from the selected memory cell as being uncorrectable via the error correction codes.

16. A memory array comprising:
one or more memory cells to store data and corresponding error correction codes;
an error correction component configured to identify errors in codewords and to correct the errors in the codewords;
a first circuit configured to generate a reference signal;
a second circuit configured to generate a self-reference signal; and
a sense output circuit configured to:
perform a first comparison of the reference signal and a first value read from a selected memory cell of the memory array, the first value read being associated with a first read operation;
detect an error in the first value read from the selected memory cell as being uncorrectable via the error correction codes; and
perform, after the first comparison and based at least in part on the error, a second comparison of the self-reference signal and a second value read from the selected memory cell of the memory array, the second value being associated with a second read operation.

17. The memory array of claim 16 , wherein the sense output circuit is further configured to:
output a data digit based on a select signal and the second comparison.

18. A memory array comprising:
one or more memory cells to store data and corresponding error correction codes;
an error correction component configured to identify errors in codewords and to correct the errors in the codewords;
a first circuit configured to generate a reference signal;
a second circuit configured to generate a self-reference signal; and
a sense output circuit configured to:
perform a first comparison of the reference signal and a first value read from a selected memory cell of the memory array, the first value read being associated with a first read operation;
detect a number of errors in the first value read from the selected memory cell associated with the first comparison including a threshold number of errors; and
perform, after the first comparison and based at least in part on the number of errors, a second comparison of the self-reference signal and a second value read from the selected memory cell of the memory array, the second value being associated with a second read operation.

19. The memory array of claim 18 , wherein the threshold number of errors is greater than 1.

20. The memory array of claim 18 , wherein the sense output circuit is further configured to:
output a data digit based on a select signal and at least one of the first comparison or the second comparison.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Kinney Wayne
• Sandhu Gurtej S

Classifications

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/1677

  Verifying circuits or methods · CPC title