Surface potential barrier for surface loss reduction at mesa sidewalls of micro-LEDs

Patent metadata

Field	Value
Publication number	US-11784287-B2
Application number	US-202117331306-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	May 26, 2021
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A micro-light emitting diode includes a mesa structure that includes a first set of one or more semiconductor layers, an active layer configured to emit light, a second set of one or more semiconductor layers on the active layer, and a dielectric layer in sidewall regions of the mesa structure. A center region of the second set of one or more semiconductor layers is thicker than a sidewall region of the second set of one or more semiconductor layers, such that a distance from a surface of the sidewall region of the second set of one or more semiconductor layers to the active layer is less than a distance from a surface of the center region of the second set of one or more semiconductor layers to the active layer, thereby forming a surface potential-induced lateral potential barrier at a sidewall region of the active layer.

First claim

What is claimed is:

1. A micro-light emitting diode (micro-LED) device comprising a mesa structure, the mesa structure comprising:
a first set of one or more semiconductor layers;
an active layer on the first set of one or more semiconductor layers and configured to emit light;
a second set of one or more semiconductor layers on the active layer; and
a dielectric layer in sidewall regions of the mesa structure,
wherein a first thickness of a center region of the second set of one or more semiconductor layers is higher than a second thickness of a sidewall region of the second set of one or more semiconductor layers, such that a distance from a surface of the sidewall region of the second set of one or more semiconductor layers to the active layer is less than a distance from a surface of the center region of the second set of one or more semiconductor layers to the active layer to form a surface potential-induced lateral potential barrier at a sidewall region of the active layer caused by a surface potential at the sidewall region of the second set of one or more semiconductor layers;
wherein the second set of one or more semiconductor layers includes a p-type semiconductor layer and an undoped or unintentionally doped semiconductor layer between the p-type semiconductor layer and the active layer; and
wherein the p-type semiconductor layer is partially or fully removed at the sidewall region of the second set of one or more semiconductor layers to form a step structure.

2. The micro-LED device of claim 1 , further comprising a metal layer formed on the dielectric layer and the center region of the second set of one or more semiconductor layers and configured to apply a voltage signal to the second set of one or more semiconductor layers at the center region of the second set of one or more semiconductor layers and at the sidewall region of the second set of one or more semiconductor layers through the dielectric layer.

3. The micro-LED device of claim 1 , wherein:
the p-type semiconductor layer is fully removed at the sidewall region of the second set of one or more semiconductor layers to form the step structure.

4. The micro-LED device of claim 1 , wherein the undoped or unintentionally doped semiconductor layer is at least partially removed at the sidewall region of the second set of one or more semiconductor layers.

5. The micro-LED device of claim 1 , wherein a thickness of the undoped or unintentionally doped semiconductor layer at the sidewall region of the second set of one or more semiconductor layers is between 5 nm and 1000 nm.

6. The micro-LED device of claim 1 , wherein:
the active layer is configured to emit red light;
the p-type semiconductor layer includes p-doped In(Ga 1-x Al x )P; and
the undoped or unintentionally doped semiconductor layer includes In(Ga 1-y Al y )P, wherein y is equal to or less than x.

7. The micro-LED device of claim 6 , wherein:
x is between 0.5 and 1.0; and
y is between 0.3 and 1.0.

8. The micro-LED device of claim 6 , wherein a molar fraction of In in the second set of one or more semiconductor layers is between 0.3 and 0.7 of a total molar fraction of In, Ga, and Al in the second set of one or more semiconductor layers.

9. The micro-LED device of claim 6 , wherein a molar fraction of In in the second set of one or more semiconductor layers is between 0.45 and 0.55 of a total molar fraction of In, Ga, and Al in the second set of one or more semiconductor layers.

10. The micro-LED device of claim 1 , wherein:
a width of the mesa structure at the active layer is between 0.5 μm and 30 μm; and
a width of the sidewall region of the second set of one or more semiconductor layers having the second thickness is smaller than the width of the mesa structure at the active layer and is between 0.1 μm and 5 μm.

11. The micro-LED device of claim 1 , wherein the sidewall region of the second set of one or more semiconductor layers having the second thickness is at a distance greater than zero from a sidewall of the mesa structure.

12. The micro-LED device of claim 1 , wherein a height of the surface potential-induced lateral potential barrier at the sidewall region of the active layer is about a half of a hand gap energy of a quantum well layer of the active layer.

13. A micro-light emitting diode (micro-LED) comprising:
a substrate;
a mesa structure on the substrate and characterized by a linear lateral dimension between 0.5 μm and 30 μm, the mesa structure including:
a first set of one or more semiconductor layers;
an active layer on the first set of one or more semiconductor layers and configured to emit red light; and
a second set of one or more semiconductor layers on the active layer, wherein at least a portion of a sidewall region of the second set of one or more semiconductor layers is removed to reduce a thickness of the sidewall region of the second set of one or more semiconductor layers;

a dielectric layer formed on the sidewall region of the second set of one or more semiconductor layers that has the reduced thickness to form a dielectric-semiconductor interface that is at an angle less than 60° with respect to an interface between the active layer and the second set of one or more semiconductor layers; and
a metal layer formed on the dielectric layer and a center region of the second set of one or more semiconductor layers and configured to apply a voltage signal to the second set of one or more semiconductor layers at the center region of the second set of one or more semiconductor layers and at the sidewall region of the second set of one or more semiconductor layers through the dielectric layer.

14. The micro-LED of claim 13 , wherein the second set of one or more semiconductor layers includes at least one of:
a p-doped semiconductor layer; or
an undoped or unintentionally doped semiconductor layer.

15. The micro-LED of claim 13 , wherein the sidewall region of the second set of one or more semiconductor layers having the reduced thickness is at a distance greater than zero from a sidewall of the mesa structure.

16. The micro-LED of claim 13 , wherein a width of the sidewall region of the second set of one or more semiconductor layers having the reduced thickness is between 0.1 μm and 5 μm.

17. The micro-LED of claim 13 , wherein a thickness of the sidewall region of the second set of one or more semiconductor layers having the reduced thickness is between 5 nm and 1 μm.

18. A micro-light emitting diode (micro-LED) device comprising:
a mesa structure comprising:
a first set of one or more semiconductor layers;
an active layer on the first set of one or more semiconductor layers and configured to emit light; and
a second set of one or more semiconductor layers on the active layer;

a dielectric layer in sidewall regions of the mesa structure; and
a metal layer formed on the dielectric layer and the second set of one or more semiconductor layers,
wherein a first thickness of a center region of the second set of one or more semiconductor layers is higher than a second thickness of a sidewall region of the second set of one or more semiconductor layers, such that a distance from a surface of the sidewall region of the second set of one or more semiconductor layers to the active layer is less than a distance from a surface of the center region of the second set of one or more semiconductor layers to the active layer to form a surface potential-induced lateral potential barrier at a sidewall region of the active layer caused by a surface potential at the sidewall region of the sec

Assignees

• Meta Platforms Tech Llc

Inventors

• Tonkikh Alexander
• Grundmann Michael
• Franke Alexander

Classifications

• H10H20/841

  Reflective coatings, e.g. dielectric Bragg reflectors · CPC title

• H10H20/824

  comprising only Group III-V materials, e.g. GaP · CPC title

• H10H20/812

  within the light-emitting regions, e.g. having quantum confinement structures · CPC title

• H10H20/821 Primary

  of the light-emitting regions, e.g. non-planar junctions · CPC title

• H10H20/819

  characterised by their shape, e.g. curved or truncated substrates · CPC title