System and method for secure, fast communications between processors on complex chips

US11782879B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11782879-B2
Application numberUS-202117234007-A
CountryUS
Kind codeB2
Filing dateApr 19, 2021
Priority dateOct 30, 2017
Publication dateOct 10, 2023
Grant dateOct 10, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A system and method for fast communication between processors on complex chips using encoding, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for secure and fast communication between processors on complex chips, comprising: a complex chip comprising at least two processors and a memory for each processor; wherein each of a first processor and a second processor on the complex chip stores a pre-trained reference codebook embedded as firmware in its respective memory, wherein: the pre-trained reference codebook is generated by using training data to identify chunklets and their associated codewords, and storing the associated codewords in the pre-trained reference codebook; and codewords within the pre-trained reference codebook are assigned such that more frequently-occurring chunklets are assigned shorter codewords based on a combination of: an observed frequency of occurrence of chunklets in the training data; and an estimated frequency of occurrence of chunklets not in the training; wherein each of a first processor and a second processor on the complex chip stores a deconstruction algorithm embedded as firmware in in its respective memory, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to: receive data; deconstruct the data into a plurality of chunklets; and encode the data by retrieving the codeword for each chunklet from the pre-trained reference codebook; and wherein each of a first processor and a second processor on the complex chip stores a reconstruction algorithm embedded as firmware in in its respective memory, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to: receive a codeword; retrieve a chunklet for each received codeword from the pre-trained reference codebook; and assemble the chunklets to reconstruct the data. 2. A method for secure and fast communication between processors on complex chips, comprising the steps of: storing a pre-trained reference codebook embedded as firmware in the memory of a first processor and in the memory of a second processor, wherein: the pre-trained reference codebook is generated by using training data that identifies chunklets and their associated codewords, and storing the associated codewords in the pre-trained reference codebook; and codewords within the pre-trained reference codebook are assigned such that more frequently-occurring chunklets are assigned shorter codewords based on a combination of: an observed frequency of occurrence of chunklets in the training data; and an estimated frequency of occurrence of chunklets not in the training; storing a deconstruction algorithm embedded as firmware in the memory of the first processor-and in the memory of the second processor, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to: receive data; deconstruct the data into a plurality of chunklets; and encode the data by retrieving the codeword for each chunklet from the pre-trained reference codebook; and storing a reconstruction algorithm embedded as firmware in the memory of the first processor and in the memory of the second processor, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to: receiving a codeword; retrieving the chunklet for each received codeword from the pre-trained reference codebook; and assembling the chunklets to reconstruct the data.

Assignees

Inventors

Classifications

  • based on file chunks · CPC title

  • Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • Saving storage space on storage systems · CPC title

  • De-duplication techniques · CPC title

  • by securing the transmission between two devices or processes · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11782879B2 cover?
A system and method for fast communication between processors on complex chips using encoding, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in…
Who is the assignee on this patent?
Atombeam Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G06F16/1752. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 10 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).