Arithmetic processing device and arithmetic processing method

Patent metadata

Field	Value
Publication number	US-11782708-B2
Application number	US-202217729025-A
Country	US
Kind code	B2
Filing date	Apr 26, 2022
Priority date	Jul 7, 2021
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time.

First claim

What is claimed is:

1. An arithmetic processing device comprising:
a memory; and
a processor coupled to the memory and configured to:
execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings;
measure a processing time of each of the plurality of pipeline stages;
set a priority of the plurality of pipeline stages in a descending order of the measured processing time; and
change the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor.

2. The arithmetic processing device according to claim 1 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes.

3. The arithmetic processing device according to claim 1 , wherein the processor hooks a function which generates a queue with no priority by the application programmable interface of the driver and a function which generates a queue with a priority by the application programmable interface of the driver.

4. An arithmetic processing method comprising:
executing, by a processor, a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings;
measuring a processing time of each of the plurality of pipeline stages;
setting a priority of the plurality of pipeline stages in a descending order of the measured processing time; and
changing the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor.

5. The arithmetic processing method according to claim 4 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes.

6. The arithmetic processing method according to claim 4 , wherein a function which generates a queue with no priority by the application programmable interface of the driver and a function which generates a queue with a priority by the application programmable interface of the driver are hooked.

Assignees

• Fujitsu Ltd

Inventors

• Kasagi Akihiko

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/3869 Primary

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title