Array substrate and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-11782317-B2
Application number	US-202017050423-A
Country	US
Kind code	B2
Filing date	Jul 9, 2020
Priority date	May 13, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

An array substrate and a liquid crystal display panel are provided. The array substrate includes a substrate, a thin film transistor layer disposed on the substrate, and a pixel electrode disposed on the thin film transistor layer. The thin film transistor layer includes a plurality of data lines. The pixel electrode includes a first trunk electrode and a second trunk electrode. Portions of the data line corresponding to the first trunk electrode and the second trunk electrode overlap or partially overlap with the first trunk electrode and the second trunk electrode.

First claim

What is claimed is:

1. An array substrate, comprising: a substrate, a thin film transistor layer disposed on the substrate, and a plurality of pixel electrodes disposed on the thin film transistor layer;
wherein the thin film transistor layer comprises a plurality of thin film transistors, a plurality of scan lines extending in a horizontal direction, and a plurality of data lines extending in a vertical direction;
wherein the array substrate comprises a plurality of sub-pixel regions, and each of the sub-pixel regions comprises a main region and a sub-region;
wherein each of the pixel electrodes corresponds to the main region and the sub-region of a same one of the sub-pixel regions, and each of the pixel electrodes comprises a first trunk electrode corresponding to the main region and a second trunk electrode corresponding to the sub-region; and
wherein one of the data lines corresponds to the first trunk electrode and the second trunk electrode, and portions of the data line corresponding to the first trunk electrode and the second trunk electrode overlap or partially overlap with the first trunk electrode and the second trunk electrode;
wherein each of the sub-pixel regions is provided with one of the thin film transistors, each of the thin film transistors are disposed between a corresponding main region and a corresponding sub-region, a drain of each of the thin film transistors is simultaneously and directly connected to a part of one of the pixel electrodes corresponding to the main region and a part of one of the pixel electrodes corresponding to the sub-region, and a source of each of the thin film transistors is connected to corresponding one of the data lines.

2. The array substrate as claimed in claim 1 , wherein a portion of the data line corresponding to the first trunk electrode overlaps with a first dark area; and
a portion of the data line corresponding to the second trunk electrode overlaps with a second dark area.

3. The array substrate as claimed in claim 1 , wherein the first trunk electrode comprises a first sub-trunk electrode and a second sub-trunk electrode which are arranged perpendicularly to each other, and the second trunk electrode comprises a third sub-trunk electrode and a fourth sub-trunk electrode which are arranged perpendicularly to each other; and
the main region is divide into four liquid crystal alignment regions by the first sub-trunk electrode and the second sub-trunk electrode, and the sub-region is divide into four liquid crystal alignment regions by the third sub-trunk electrode and the fourth sub-trunk electrode.

4. The array substrate as claimed in claim 3 , wherein a portion of the data line corresponding to the first sub-trunk electrode overlaps or partially overlaps with the first sub-trunk electrode, and a portion of the data line corresponding to the third sub-trunk electrode overlaps or partially overlaps with the third sub-trunk electrode.

5. The array substrate as claimed in claim 1 , wherein each of the pixel electrodes further comprises a first branch electrode corresponding to the main region and a second branch electrode corresponding to the sub-region, wherein the first branch electrode and the first trunk electrode are electrically connected at a first predetermined angle, the second branch electrode and the second trunk electrode are electrically connected at a second predetermined angle, and the first predetermined angle is different from the second predetermined angle.

6. The array substrate as claimed in claim 5 , wherein first predetermined angles between the corresponding first branch electrode and the first trunk electrode of two adjacent sub-pixel regions are the same; and
second predetermined angles between the corresponding second branch electrode and the second trunk electrode of two adjacent sub-pixel regions are different, or the second predetermined angles between the corresponding second branch electrode and the second trunk electrode of two adjacent sub-pixel regions are the same.

7. The array substrate as claimed in claim 6 , wherein the first predetermined angle ranges from 10° to 45°, and the second predetermined angle ranges from 5° to 15°.

8. A liquid crystal display panel, comprising the array substrate as claimed in claim 1 , an opposite substrate opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate.

9. An array substrate, comprising: a substrate, a thin film transistor layer disposed on the substrate, and a plurality of pixel electrodes disposed on the thin film transistor layer;
wherein the thin film transistor layer comprises a plurality of thin film transistors, a plurality of scan lines extending in a horizontal direction, and a plurality of data lines extending in a vertical direction;
wherein the array substrate comprises a plurality of sub-pixel regions, and each of the sub-pixel regions comprises a main region and a sub-region;
wherein each of the pixel electrodes corresponds to the main region and the sub-region of a same one of the sub-pixel regions, and each of the pixel electrodes comprises a first trunk electrode corresponding to the main region and a second trunk electrode corresponding to the sub-region;
wherein the sub-pixel regions are divided into eight liquid crystal alignment regions by the first trunk electrode and the second trunk electrode;
the main region comprises a first dark area disposed between two of the liquid crystal alignment regions and overlapping or partially overlapping with the first trunk electrode, and the sub-region comprises a second dark area disposed between two of the liquid crystal alignment regions and overlapping or partially overlapping with the second trunk electrode; and
wherein one of the data lines corresponds to the first trunk electrode and the second trunk electrode, and portions of the data line corresponding to the first trunk electrode and the second trunk electrode overlap or partially overlap with the first trunk electrode and the second trunk electrode;
wherein each of the sub-pixel regions is provided with one of the thin film transistors, each of the thin film transistors are disposed between a corresponding main region and a corresponding sub-region, a drain of each of the thin film transistors is simultaneously and directly connected to a part of one of the pixel electrodes corresponding to the main region and a part of one of the pixel electrodes corresponding to the sub-region, and a source of each of the thin film transistors is connected to corresponding one of the data lines.

10. The array substrate as claimed in claim 9 , wherein a portion of the data line corresponding to the first trunk electrode overlaps with the first dark area; and
a portion of the data line corresponding to the second trunk electrode overlaps with the second dark area.

11. The array substrate as claimed in claim 9 , wherein the first trunk electrode comprises a first sub-trunk electrode and a second sub-trunk electrode which are arranged perpendicularly to each other, and the second trunk electrode comprises a third sub-trunk electrode and a fourth sub-trunk electrode which are arranged perpendicularly to each other; and
the main region is divide into four liquid crystal alignment regions by the first sub-trunk electrode and the second sub-trunk electrode, and the sub-region is divide into four liquid crystal alignment regions by the third sub-trunk electrode and the fourth sub-trunk electrode.

12. The array substrate as claimed in claim 11 , wherein a portion of the data line corresponding to the first sub-trunk electrode overlaps or partially overlaps with the first sub-

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Zhang Yihe

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/134345 Primary

  Subdivided pixels, e.g. for grey scale or redundancy · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title