Digital fingerprint generation circuit, generation method and electronic device

Patent metadata

Field	Value
Publication number	US-11777541-B2
Application number	US-202117330561-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	Aug 7, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Embodiments of the present disclosure provide a circuit and a method for digital fingerprint generation, and an electronic device. The digital fingerprint generation method includes inputting an input signal from outside; generating a frequency relationship indication signal between an input signal and a feedback signal; generating a frequency control signal based on the frequency relationship indication signal; generating an intermediate signal based on a frequency control signal and pulse signals; dividing the intermediate signal in frequency to generate the feedback signal; and generating a digital fingerprint based on the input signal and the feedback signal.

First claim

The invention claimed is:

1. A digital fingerprint generation circuit, comprising:
a pulse generation sub-circuit configured to generate a plurality of pulse signals;
a digital control oscillator sub-circuit configured to generate an intermediate signal based on a frequency control signal and the plurality of pulse signals;
a frequency dividing sub-circuit configured to divide the intermediate signal in frequency to generate a feedback signal;
a frequency and phase detection sub-circuit configured to generate a digital fingerprint based on an input signal and the feedback signal, and further configured to generate a frequency indication signal indicating whether a frequency of the input signal is larger than a frequency of the feedback signal; and
a control sub-circuit configured to generate the frequency control signal based on the frequency indication signal,
wherein the input signal is a signal generated by a pulse generator, and
wherein the input signal has a frequency not within an operating frequency range of the digital control oscillator sub-circuit.

2. The digital fingerprint generation circuit according to claim 1 , wherein the frequency and phase detection sub-circuit is further configured to generate the frequency indication signal by generating a phase relationship indication signal between the input signal and the feedback signal.

3. The digital fingerprint generation circuit according to claim 1 , wherein the pulse generation sub-circuit is a ring oscillator comprising a NAND gate.

4. The digital fingerprint generation circuit according to claim 1 , wherein:
the digital control oscillator sub-circuit comprises a logic control sub-circuit, an input terminal, and an output terminal;
the logic control sub-circuit is configured to generate a selection signal based on the frequency control signal;
the input terminal is configured to receive the plurality of pulse signals and the selection signal, and select and synthesize among the plurality of pulse signals based on the selection signal to generate a synthesized signal; and
the output terminal comprises a trigger circuit configured to receive the synthesized signal and generate the intermediate signal based on the synthesized signal and a clock signal.

5. The digital fingerprint generation circuit according to claim 4 , wherein:
the logic control sub-circuit comprises a first adder, a second adder, a first register, a second register, a third register, and a fourth register;
the input terminal comprises a first K→1 multiplexer, a second K→1 multiplexer and a 2→1 multiplexer, where K is an integer multiple of 2, the first K→1 multiplexer and the second K→1 multiplexer receive respectively K pulses output by the pulse generation sub-circuit, and the 2→1 multiplexer receives signals from the first K→1 multiplexer and the second K→1 multiplexer and also a first clock signal for synthesizing and sending to the output terminal; and
the trigger circuit comprises a D flip-flop, a first inverter and a second inverter, where the D flip-flop receives a signal from the 2→1 multiplexer, the first inverter receives the first clock signal and outputs a signal to the D flip-flop, and the second inverter receives the first clock signal and outputs a second clock signal.

6. The digital fingerprint generation circuit according to claim 1 , wherein the frequency and phase detection sub-circuit comprises:
a first input terminal configured to receive the input signal;
a second input terminal configured to receive the feedback signal;
a frequency divider configured to divide the input signal in frequency;
a register sub-circuit configured to obtain a plurality of signal values for an output signal from the frequency divider at a plurality of edges of the feedback signal;
an output terminal configured to output the digital fingerprint; and
a logic sub-circuit configured to perform logic operations on the plurality of signal values output by the register sub-circuit, and generate the frequency indication signal.

7. The digital fingerprint generation circuit according to claim 6 , wherein:
the register sub-circuit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop;
an input end of the first D flip-flop and an input end of the third D flip-flop are both connected to an output end of the frequency divider;
an input end of the second D flip-flop is connected to an output end of the first D flip-flop;
an input end of the fourth D flip-flop is connected to an output end of the third D flip-flop;
a clock end of the first D flip-flop, a clock end of the second D flip-flop and a clock end of the fourth D flip-flop are all connected to the second input terminal; and
a clock end of the third D flip-flop is connected to the second input terminal through a first NOT gate.

8. The digital fingerprint generation circuit according to claim 6 , wherein:
the logic sub-circuit comprises a first logic sub-circuit and a second logic sub-circuit;
the first logic sub-circuit comprises a first XOR gate and a second XOR gate, wherein two input ends of the first XOR gate are respectively connected to an output end of the second D flip-flop and an output end of the fourth D flip-flop, two input ends of the second XOR gate are respectively connected to an output end of the first D flip-flop and an output end of the fourth D flip-flop, an output end of the second XOR gate is connected to the second output terminal, and an output end of the first XOR gate is connected to the third output terminal; and
the second logic sub-circuit comprises a second NOT gate, a third NOT gate, a first AND gate and a second AND gate, wherein two input ends of the first AND gate are respectively connected to the second output terminal and the third output terminal, one of input ends of the second AND gate is connected to the third output terminal through the second NOT gate, and the other of the output ends of the second AND gate is connected to the second output terminal through the third NOT gate.

9. The digital fingerprint generation circuit according to claim 6 , wherein the register sub-circuit comprises a D flip-flop connected to the frequency divider, and the D flip-flop is configured to output the digital fingerprint based on an output signal of the frequency divider.

10. A digital fingerprint generation method, comprising:
inputting an input signal from outside;
generating a frequency indication signal indicating whether a frequency of the input signal is larger than a frequency of a feedback signal;
generating a frequency control signal based on the frequency indication signal;
generating an intermediate signal based on the frequency control signal and pulse signals;
dividing the intermediate signal in frequency to generate the feedback signal; and
generating a digital fingerprint based on the input signal and the feedback signal,
wherein the input signal is a signal generated by a pulse generator, and
wherein the input signal has a frequency not within an operating frequency range of a digital control oscillator sub-circuit.

11. The digital fingerprint generation method according to claim 10 , wherein the frequency indication signal is generated by generating a phase relationship indication signal between the input signal and the feedback signal.

12. The digital fingerprint generation method according to claim 10 , further comprising performing a Fourier transform on the digital fingerprint to generate a visualized digital fingerprint.

13. An electronic device, comprising:
a digital fingerprint generation circuit, wherein the digital fingerprint generation circuit

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title

• H03K3/3562 Primary

  of the primary-secondary type · CPC title