Method of forming backside power rails

Patent metadata

Field	Value
Publication number	US-11777016-B2
Application number	US-202217811266-A
Country	US
Kind code	B2
Filing date	Jul 7, 2022
Priority date	Sep 29, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first bottom semiconductor feature and a second bottom semiconductor feature disposed on a backside dielectric layer;
a first vertical stack of nanostructures disposed over the first bottom semiconductor feature;
a second vertical stack of nanostructures disposed over the second bottom semiconductor feature;
a first epitaxial source/drain feature extending between the first vertical stack of nanostructures and the second vertical stack of nanostructures along a direction; and
a backside contact extending through the backside dielectric layer to couple to the first epitaxial source/drain feature,
wherein a portion of the backside contact extends between the first bottom semiconductor feature and the second bottom semiconductor feature along the direction.

2. The semiconductor structure of claim 1 , further comprising:
a second epitaxial source/drain feature coupled to sidewalls of the first vertical stack of nanostructures such that the first vertical stack of nanostructures extends between the first epitaxial source/drain feature and the second epitaxial source/drain feature,
wherein the second epitaxial source/drain feature is spaced apart from the backside dielectric layer by a portion of the first bottom semiconductor feature.

3. The semiconductor structure of claim 1 , further comprising:
a first gate structure wrapping around each of the first vertical stack of nanostructures; and
a second gate structure wrapping around each of the second vertical stack of nanostructures.

4. The semiconductor structure of claim 1 , further comprising:
a silicide layer sandwiched between the first epitaxial source/drain feature and the backside contact.

5. The semiconductor structure of claim 4 , wherein the silicide layer comprises titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi).

6. The semiconductor structure of claim 4 , wherein the silicide layer comprises titanium germanide (TiGe), titanium germanide nitride (TiGeN), tantalum germanide (TaGe), tungsten germanide (WGe), cobalt germanide (CoGe), or nickel germanide (NiGe).

7. The semiconductor structure of claim 1 , wherein the backside contact comprises aluminum (Al), rhodium (Rh), ruthenium (Ru), copper (Cu), iridium (Ir), or tungsten (W).

8. The semiconductor structure of claim 1 , wherein the backside dielectric layer comprises silicon oxide.

9. A method, comprising:
receiving a composite substrate that includes:
a semiconductor substrate,
a first silicon germanium (SiGe) layer over the semiconductor substrate,
a first silicon (Si) layer over the first silicon germanium (SiGe) layer,
a second SiGe layer over the first Si layer, and
a second Si layer over the second SiGe layer;

patterning the second Si layer to form a fin;
forming a dummy gate stack over a channel region of the fin;
recessing a source region and a drain region of the fin to form a source opening and a drain opening, the source region and the drain region sandwiching the channel region;
depositing a mask film over the source opening, the dummy gate stack and the drain region;
patterning the mask film to expose the source opening;
after the patterning of the mask film, selectively extending the source opening through the second SiGe layer to form an extended source opening;
with the patterned mask film in place, forming a semiconductor plug in the extended source opening;
forming an epitaxial source feature over the semiconductor plug and an epitaxial drain feature in the drain opening;
planarizing the composite substrate from a surface of the semiconductor substrate until the semiconductor plug is exposed;
after the planarizing, replacing the second SiGe layer with a backside dielectric layer; and
replacing the semiconductor plug with a backside contact.

10. The method of claim 9 , wherein the semiconductor substrate comprises silicon, germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond.

11. The method of claim 9 ,
wherein the first SiGe layer comprises a first thickness,
wherein the first Si layer comprises a second thickness,
wherein the second SiGe layer comprises a third thickness,
wherein the second Si layer comprises a fourth thickness,
wherein the fourth thickness is smaller than the third thickness,
wherein the first thickness is greater than the second thickness.

12. The method of claim 11 ,
wherein the first thickness is between about 25 nm and about 30 nm,
wherein the second thickness is between about 5 nm and about 15 nm,
wherein the third thickness is between about 30 nm and about 35 nm,
wherein the fourth thickness is between about 50 nm and about 100 nm.

13. The method of claim 9 , wherein the mask film comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or silicon oxycarbide.

14. The method of claim 9 , further comprising:
before the forming of the epitaxial source feature and the epitaxial drain feature, removing the mask film.

15. The method of claim 9 , wherein the semiconductor plug comprises silicon germanium.

16. The method of claim 15 , wherein a germanium content in the semiconductor plug is smaller than a germanium content in the second SiGe layer.

17. The method of claim 9 , wherein the replacing of the second SiGe layer comprises:
selectively removing the second SiGe layer using a wet etch process without substantially damaging the semiconductor plug; and
after the selectively removing, depositing the backside dielectric layer over the semiconductor plug.

18. A method, comprising:
receiving a composite substrate that includes:
a semiconductor substrate,
a first silicon germanium (SiGe) layer over the semiconductor substrate,
a silicon (Si) layer over the first silicon germanium (SiGe) layer,
a second SiGe layer over the Si layer, and
a semiconductor layer stack over the second SiGe layer, the semiconductor layer stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;

patterning the semiconductor layer stack to form a fin-shaped structure;
forming a dummy gate stack over a channel region of the fin-shaped structure;
recessing a source region and a drain region of the fin-shaped structure to form a source opening and a drain opening, the source region and the drain region sandwiching the channel region;
depositing a mask film over the source opening, the dummy gate stack and the drain region;
patterning the mask film to expose the source opening;
after the patterning of the mask film, selectively extending the source opening through the second SiGe layer to form an extended source opening;
with the patterned mask film in place, forming a semiconductor plug in the extended source opening;
forming an epitaxial source feature over the semiconductor plug and an epitaxial drain feature in the drain opening;
planarizing the composite substrate from a surface of the semiconductor substrate until the semiconductor plug is exposed;
after the planarizing, replacing the second SiGe layer with a backside dielectric layer; and
replacing the semiconductor plug with a backside contact.

19. The method of claim 18 , further comprising:
after the recessing, partially and selectively etching sidewalls of the plurality of sacrificial layers to form inner spacer recesses; and
forming inner spacer features in the inner spacer recesses.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Ping-Wei
• Yang Chih-Chuan
• Lin Yu-Kuan
• Yeap Choh Fei

Classifications

• H10W72/07341

  Controlling the bonding environment, e.g. atmosphere composition or temperature · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title