Display device

Patent metadata

Field	Value
Publication number	US-11776970-B2
Application number	US-202117353451-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jun 30, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Disclosed is a display device including a substrate including display and non-display areas, a first thin-film transistor located in the non-display area, and second and third thin-film transistors located in the display area. The first thin-film transistor includes a first semiconductor pattern, a first gate electrode overlapping the first semiconductor pattern, and first source and first drain electrodes connected to the first semiconductor pattern. The second thin-film transistor includes second and third semiconductor patterns including a first oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a third gate electrode overlapping the third semiconductor pattern, and second source and second drain electrodes connected to the second and third semiconductor patterns. The third thin-film transistor includes a fourth semiconductor pattern including a first oxide semiconductor, a fourth gate electrode overlapping the fourth semiconductor pattern, and third source and third drain electrodes connected to the fourth semiconductor pattern.

First claim

What is claimed is:

1. A display device comprising:
a substrate comprising a display area and a non-display area;
a first thin-film transistor located in the non-display area; and
a second thin-film transistor and a third thin-film transistor located in the display area,
wherein the first thin-film transistor comprises:
a first semiconductor pattern comprising a first poly silicon;
a first gate electrode overlapping the first semiconductor pattern; and
a first source electrode and a first drain electrode connected to the first semiconductor pattern,

wherein the second thin-film transistor comprises:
a second semiconductor pattern and a third semiconductor pattern comprising a first oxide semiconductor;
a second gate electrode overlapping the second semiconductor pattern;
a third gate electrode overlapping the third semiconductor pattern;
a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through a contact hole;
a first insulation film provided between the second semiconductor pattern and the second gate electrode; and
a second insulation film provided between the second semiconductor pattern and the first insulation film, wherein the first insulation film has a higher hydrogen particle content than the second insulation film, and

wherein the third thin-film transistor comprises:
a fourth semiconductor pattern comprising a first oxide semiconductor;
a fourth gate electrode overlapping the fourth semiconductor pattern; and
a third source electrode and a third drain electrode connected to the fourth semiconductor pattern.

2. The display device according to claim 1 , wherein the second semiconductor pattern and the third semiconductor pattern are connected in parallel through the second source electrode and the second drain electrode.

3. The display device according to claim 1 , wherein the second semiconductor pattern and the third semiconductor pattern overlap each other.

4. The display device according to claim 3 , wherein the second semiconductor pattern comprises a second source region and a second drain region, the second source electrode and the second drain electrode in contact with the second source region and the second drain region, and
wherein the third semiconductor pattern comprises a third source region and a third drain region, the second source electrode and the second drain electrode in contact with the third source region and the third drain region.

5. The display device according to claim 4 , wherein each of the second source region, the second drain region, the third source region, and the third drain region is doped using a dopant and includes a conductorized region.

6. The display device according to claim 5 , wherein, when the conductorized region of the second semiconductor pattern is denoted by L1 and the conductorized region of the third semiconductor pattern is denoted by L2, a length of L1 in a channel direction is set to be greater than a length of L2 in the channel direction.

7. The display device according to claim 5 , wherein the dopant comprises at least one of boron (B), phosphorus (P), fluorine (F), or hydrogen (H).

8. The display device according to claim 1 , wherein a value of driving current of the second thin-film transistor is greater than a value of driving current of the third thin-film transistor, the value of the driving region corresponding to a saturation region in an Ids-Vgs curve.

9. The display device according to claim 1 , wherein a value of a ratio of variation in current to variation in voltage of the second thin-film transistor is greater than an S-factor of the third thin-film transistor, where the value is a S-factor.

10. A display device comprising:
a substrate comprising a display area and a non-display area;
a driving circuit unit located in the non-display area; and
a pixel unit located in the display area,
wherein the pixel unit comprises a switching transistor and a driving transistor configured to have different respective structures,
wherein the driving transistor comprises:
a first active layer comprising source and drain regions and a channel region;
a second active layer located above the first active layer;
source and drain electrodes located above the second active layer, the source and drain electrodes being connected to the source and drain regions of the first active layer and source and drain regions of the second active layer;
a lower gate electrode located below the first active layer; and
an upper gate electrode located above the second active layer,
wherein the source and drain regions of the first active layer are connected to the source and drain electrodes through a first contact hole,
wherein the source and drain regions of the second active layer are connected to the source and drain electrodes through a second contact hole, and
wherein the first contact hole is located farther away from the upper gate electrode than the second contact hole.

11. The display device according to claim 10 , wherein the driving transistor is configured such that the first active layer and the second active layer are connected in parallel through the source and drain electrodes.

12. The display device according to claim 10 , wherein the first active layer and the second active layer overlap each other.

13. The display device according to claim 10 , wherein, when a spacing distance from the lower gate electrode to the first contact hole is denoted by L4 and a spacing distance from the lower gate electrode to the second contact hole is denoted by L3, L4 is set to be greater than L3.

14. The display device according to claim 10 , wherein each of the source and drain regions of the first active layer and the source and drain regions of the second active layer is doped using a dopant and includes a conductorized region.

15. The display device according to claim 14 , wherein when a length of the conductorized region of the first active layer in a channel direction is denoted by L1 and a length of the conductorized region of the second active layer in the channel direction is denoted by L2, L1 is set to be greater than L2.

16. The display device according to claim 14 , wherein the dopant comprises at least one of boron (B), phosphorus (P), fluorine (F), or hydrogen (H).

17. The display device according to claim 10 , wherein each of the first active layer and the second active layer comprises an oxide semiconductor.

18. The display device according to claim 10 , wherein a value of driving current of the driving transistor of the pixel unit is greater than a value of driving current of the switching transistor of the pixel unit, wherein the value of the driving current corresponds to a saturation region in an Ids-Vgs curve.

19. The display device according to claim 10 , wherein a value of a ratio of variation in current to variation in voltage of the driving transistor of the pixel unit is greater than a S-factor of the switching transistor of the pixel unit, wherein the value is a S-factor.

Assignees

• Lg Display Co Ltd

Inventors

• Shin Sung Soo
• Ryu Won Sang
• Lee Sang Gul

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/471 Primary

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title