BiMOS semiconductor device

Patent metadata

Field	Value
Publication number	US-11776953-B2
Application number	US-202217670534-A
Country	US
Kind code	B2
Filing date	Feb 14, 2022
Priority date	Mar 31, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n + drain layer; a parallel pn layer including n − drift and p pillar layers joined alternately; a composite layer including a p base layer and an n + source layer, the n + drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n + source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n − drift layer.

First claim

What is claimed is:

1. An n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device comprising:
an n + drain layer;
a parallel pn layer comprising n − drift and p pillar layers joined alternately;
a composite layer comprising a p base layer and an n + source layer, wherein the n + drain layer, the parallel pn layer, and the composite layer are provided in order;
a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n + source layer; and
a high-resistance layer provided between the p pillar layer and the p base layer,
the p pillar layer having an impurity concentration lower than that of the n − drift layer.

2. A p-channel BiMOS semiconductor device having a trench gate structure, the p-channel BiMOS semiconductor device comprising:
a p + drain layer;
a parallel pn layer comprising p − drift and n pillar layers joined alternately;
a composite layer comprising an n base layer and a p + source layer, wherein the p + drain layer, the parallel pn layer, and the composite layer are provided in order;
a high-resistance layer provided between a portion of the n base layer above the n pillar layer and the p + source layer; and
a high-resistance layer provided between the n pillar layer and the n base layer,
the n pillar layer having an impurity concentration lower than that of the p − drift layer.

Assignees

• Honda Motor Co Ltd

Inventors

• Maeda Yasuhiro
• Tsukada Yoshinari
• Maita Shinya
• Nakamura Genki
• Negoro Yuki

Classifications

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title