Driving chip and display apparatus

Patent metadata

Field	Value
Publication number	US-11776455-B2
Application number	US-202217584867-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Dec 24, 2019
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Provided are a driver chip and a display apparatus. The driver chip includes a digital module, an analog module, and a decoupling capacitor. The digital module is configured to generate a digital signal. The analog module includes a reference voltage source and a Gamma voltage generation circuit, an output terminal of the reference voltage source is electrically connected to an input terminal of the Gamma voltage generation circuit, and the Gamma voltage generation circuit is configured to generate a Gamma voltage according to a reference voltage outputted by the reference voltage source. The decoupling capacitor is connected between the digital module and the output terminal of the reference voltage source.

First claim

What is claimed is:

1. A driver chip, comprising:
a digital signal generator;
an analog signal generator which comprises a reference voltage source and a Gamma voltage generation circuit, wherein an output terminal of the reference voltage source is electrically connected to an input terminal of the Gamma voltage generation circuit, and the Gamma voltage generation circuit is configured to generate a Gamma voltage according to a reference voltage outputted by the reference voltage source; and
a decoupling capacitor, wherein the decoupling capacitor is connected between the digital signal generator and the output terminal of the reference voltage source,
wherein the reference voltage source comprises an operational amplifier, a first voltage generation circuit, a first voltage dividing circuit, a second voltage generation circuit and a second voltage dividing circuit, and the first voltage generation circuit and the second voltage generation circuit are configured to generate voltage amounts having opposite temperature coefficients;
wherein an output terminal of the first voltage generation circuit is electrically connected to a first terminal of the first voltage dividing circuit, a second terminal of the first voltage dividing circuit is electrically connected to a non-inverting input terminal of the operational amplifier, and a third terminal of the first voltage dividing circuit is electrically connected to an output terminal of the operational amplifier;
wherein an output terminal of the second voltage generation circuit is electrically connected to a first terminal of the second voltage dividing circuit, a second terminal of the second voltage dividing circuit is electrically connected to an inverting input terminal of the operational amplifier, and a third terminal of the second voltage dividing circuit is grounded; and
wherein the output terminal of the operational amplifier is electrically connected to the input terminal of the Gamma voltage generation circuit.

2. The driver chip according to claim 1 , wherein the first voltage dividing circuit comprises a first resistor and a second resistor, and wherein a first terminal of the first resistor serves as the first terminal of the first voltage dividing circuit, a second terminal of the first resistor is electrically connected to a first terminal of the second resistor, the second terminal of the first resistor serves as the second terminal of the first voltage dividing circuit, and a second terminal of the second resistor serves as the third terminal of the first voltage dividing circuit.

3. The driver chip according to claim 2 , wherein the second voltage dividing circuit comprises a third resistor and a fourth resistor, and wherein a first terminal of the third resistor serves as the first terminal of the second voltage dividing circuit, a second terminal of the third resistor is electrically connected to a first terminal of the fourth resistor, the second terminal of the third resistor serves as the second terminal of the second voltage dividing circuit, and a second terminal of the fourth resistor serves as the third terminal of the second voltage dividing circuit.

4. The driver chip according to claim 3 , wherein a ratio of the resistance value of the second resistor to the resistance value of the first resistor is equal to a ratio of the resistance value of the fourth resistor to the resistance value of the third resistor.

5. The driver chip according to claim 1 , wherein the first voltage generation circuit comprises a first voltage source and a first triode, and wherein a base of the first triode is electrically connected to the first terminal of the first voltage dividing circuit, and a first electrode of the first triode and a second electrode of the first triode are respectively connected to the first voltage source and a ground terminal.

6. The driver chip according to claim 5 , wherein the second voltage generation circuit comprises a second voltage source and a multiplier, and wherein the second voltage source is electrically connected to a first terminal of the multiplier, and a second terminal of the multiplier is electrically connected to the first terminal of the second voltage dividing circuit.

7. The driver chip according to claim 1 , wherein the digital signal generator comprises a crystal oscillator, a timing control circuit, a level conversion circuit and a clock signal generation circuit, wherein an output terminal of the crystal oscillator is electrically connected to an input terminal of the timing control circuit, an output terminal of the timing control circuit is electrically connected to an input terminal of the level conversion circuit, an output terminal of the level conversion circuit is electrically connected to an input terminal of the clock signal generation circuit, and an output terminal of the clock signal generation circuit is configured to output a clock signal.

8. The driver chip according to claim 7 , wherein a first terminal of the decoupling capacitor is electrically connected to one of the output terminal of the crystal oscillator, the output terminal of the timing control circuit, the output terminal of the level conversion circuit and the output terminal of the clock signal generation circuit, and wherein a second terminal of the decoupling capacitor is electrically connected to the output terminal of the reference voltage source.

9. The driver chip according to claim 8 , wherein the first terminal of the decoupling capacitor is electrically connected to the output terminal of the crystal oscillator, and wherein the second terminal of the decoupling capacitor is electrically connected to the output terminal of the reference voltage source.

10. The driver chip according to claim 8 , wherein the first terminal of the decoupling capacitor is electrically connected to the output terminal of the clock signal generation circuit and the second terminal of the decoupling capacitor is electrically connected to the output terminal of the reference voltage source.

11. The driver chip according to claim 1 , wherein a capacitance value of the decoupling capacitor is from 0.2 microfarads to 5 microfarads.

12. The driver chip according to claim 7 , wherein the level conversion circuit comprises a first level conversion circuit and a second level conversion circuit, an input terminal of the first level conversion circuit is electrically connected to the output terminal of the timing control circuit, and an input terminal of the second level conversion circuit is electrically connected to the output terminal of the timing control circuit; and
wherein the clock signal generation circuit comprises a first clock signal generation circuit and a second clock signal generation circuit, an input terminal of the first clock signal generation circuit is electrically connected to an output terminal of the first level conversion circuit, an output terminal of the first clock signal generation circuit is configured to output a first clock signal, an input terminal of the second clock signal generation circuit is electrically connected to an output terminal of the second level conversion circuit, and an output terminal of the second clock signal generation circuit is configured to output a second clock signal.

13. The driver chip according to claim 12 , wherein a first terminal of the decoupling capacitor is electrically connected to the output terminal of the first clock signal generation circuit and a second terminal of the decoupling capacitor is electrically connected to the output terminal of the reference voltage source.

14. The driver chip according to claim 1 , where

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Wang Yuqing
• Chen Xinquan
• Wang Zheng
• Zhang Xiaobao

Classifications

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0673

  for control of gamma adjustment, e.g. selecting another gamma curve · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title