Integrated circuit development using machine learning-based prediction of power, performance, and area

Patent metadata

Field	Value
Publication number	US-11775720-B2
Application number	US-202117366340-A
Country	US
Kind code	B2
Filing date	Jul 2, 2021
Priority date	Jul 2, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

First claim

What is claimed is:

1. A computer-implemented method comprising:
obtaining, using a processor, values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features; and
assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

2. The computer-implemented method according to claim 1 , further comprising training the machine learning model using data from previous architecture designs of memory arrays with known PPA values.

3. The computer-implemented method according to claim 2 , wherein the training the machine learning model further comprises identifying correlated features based on the data from previous architecture designs, each of the correlated features exhibiting a correlation between a value of the correlated feature and the known PPA value.

4. The computer-implemented method according to claim 2 , wherein the training the machine learning model includes comparing a predicted PPA value, obtained by implementing the machine learning model, for each of the previous architecture designs of memory arrays with a corresponding one of the known PPA values.

5. The computer-implemented method according to claim 4 , wherein the training the machine learning model includes identifying determinative features, the determinative features being features among the data from previous architecture designs that are given highest weighting by the machine learning model.

6. The computer-implemented method according to claim 1 , wherein obtaining the predicted PPA of the memory array includes aggregating a PPA prediction from each model of an ensemble of models that make up the machine learning model.

7. The computer-implemented method according to claim 1 , wherein the machine learning model is a linear or nonlinear model.

8. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
obtaining feature values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features; and
assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

9. The system according to claim 8 , further comprising training the machine learning model using data from previous architecture designs of memory arrays with known PPA values.

10. The system according to claim 9 , wherein the training the machine learning model further comprises identifying correlated features based on the data from previous architecture designs, each of the correlated features exhibiting a correlation between a value of the correlated feature and the known PPA value.

11. The system according to claim 9 , wherein the training the machine learning model includes comparing a predicted PPA value, obtained by implementing the machine learning model, for each of the previous architecture designs of memory arrays with a corresponding one of the known PPA values.

12. The system according to claim 11 , wherein the training the machine learning model includes identifying determinative features, the determinative features being features among the data from previous architecture designs that are given highest weighting by the machine learning model.

13. The system according to claim 8 , wherein obtaining the predicted PPA of the memory array includes aggregating a PPA prediction from each model of an ensemble of models that make up the machine learning model.

14. The system according to claim 8 , wherein the machine learning model is a linear or nonlinear model.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
obtaining feature values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features; and
assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

16. The computer program product according to claim 15 , further comprising training the machine learning model using data from previous architecture designs of memory arrays with known PPA values.

17. The computer program product according to claim 16 , wherein the training the machine learning model further comprises identifying correlated features based on the data from previous architecture designs, each of the correlated features exhibiting a correlation between a value of the correlated feature and the known PPA value.

18. The computer program product according to claim 16 , wherein the training the machine learning model includes comparing a predicted PPA value, obtained by implementing the machine learning model, for each of the previous architecture designs of memory arrays with a corresponding one of the known PPA values.

19. The computer program product according to claim 18 , wherein the training the machine learning model includes identifying determinative features, the determinative features being features among the data from previous architecture designs that are given highest weighting by the machine learning model.

20. The computer program product according to claim 15 , where obtaining the predicted PPA of the memory array includes aggregating a PPA prediction from each model of an ensemble of models that make up the machine learning model.

Assignees

• IBM

Inventors

• Mahmud Tuhin
• Islam Saiful
• Mathews Abraham
• Wang Geoffrey

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06N20/20

  Ensemble learning · CPC title

• G06F30/27 Primary

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/32

  Circuit design at the digital level (reconfigurable circuits G06F30/34) · CPC title

• G06F2119/20

  Design reuse, reusability analysis or reusability optimisation · CPC title