System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

Patent metadata

Field	Value
Publication number	US-11775047-B2
Application number	US-202217879256-A
Country	US
Kind code	B2
Filing date	Aug 2, 2022
Priority date	Mar 26, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
at least one core;
a workload monitor circuit coupled to the at least one core to determine background task metric information based on a first amount of time that the at least one core executed background tasks during an active duration; and
a control circuit coupled to the workload monitor circuit to dynamically apply a power management policy for a background mode when the background task metric information exceeds a first threshold, the power management policy for the background mode to reduce power consumption of at least the processor.

2. The processor of claim 1 , wherein the power management policy comprises a power limit less than a thermal design power level of the processor.

3. The processor of claim 1 , wherein the workload monitor circuit further is to determine foreground task metric information based on a second amount of time that the at least one core executed foreground tasks during a second duration.

4. The processor of claim 3 , wherein the control circuit is to dynamically apply a power management policy for a responsiveness mode when the foreground task metric information exceeds a second threshold, the power management policy for the responsiveness mode to increase performance of at least the processor.

5. The processor of claim 4 , wherein the control circuit is to maintain a current power management policy when the foreground task metric information does not exceed the second threshold.

6. The processor of claim 3 , wherein the control circuit is to dynamically apply the power management policy for the background mode when a user did not interact with a system including the processor within an evaluation interval.

7. The processor of claim 3 , wherein the control circuit is to determine the background task metric information when a user did not interact with a system including the processor within an evaluation interval.

8. The processor of claim 1 , further comprising a hardware feedback circuit to determine feedback information comprising an energy efficiency capability and a performance capability of the at least one core.

9. The processor of claim 8 , wherein the hardware feedback circuit is to send the feedback information to a scheduler to enable the scheduler to schedule one or more background tasks to a less performant core based at least in part on the feedback information.

10. The processor of claim 1 , wherein the processor is to provide hardware capability information of a plurality of cores of the processor to a scheduler, to enable the scheduler to schedule one or more background tasks to a less performant core of the plurality of cores based at least in part on the hardware capability information.

11. A method comprising:
identifying at least one first core of a multicore processor of a system that is less performant than at least one second core of the multicore processor;
setting a background core mask to indicate an affinity of the at least one first core for background task execution;
determining whether a user of the system is present; and
in response to determining the user presence, scheduling at least one background task to the at least one first core using the background core mask.

12. The method of claim 11 , wherein the method further comprises identifying the at least one first core based at least in part on feedback information comprising energy efficiency information and performance information.

13. The method of claim 11 , wherein the method further comprises setting the background core mask having one or more values different than a default core mask.

14. The method of claim 11 , wherein the method further comprises scheduling one or more foreground tasks to the at least one second core.

15. The method of claim 14 , wherein the method further comprises in response to determining that the user is not present, scheduling the at least one background task to the at least one second core.

16. The method of claim 11 , wherein the method further comprises determining background task metric information based on a first amount of time that the multicore processor executed background tasks during an active duration.

17. The method of claim 16 , wherein the method further comprises configuring a power controller of the multicore processor with a power management policy for a background mode when the background task metric information exceeds a first threshold, the power management policy for the background mode to reduce power consumption of the multicore processor.

18. A system comprising:
a processor comprising:
a plurality of cores, including one or more first cores and one or more second cores, the one or more first cores heterogenous to the one or more second cores; and
a hardware feedback control circuit to determine first hardware feedback information for the one or more first cores and second hardware feedback information for the one or more second cores, wherein the first and second hardware feedback information comprises energy efficiency capability information and performance capability information; and
a control circuit to update a power management policy based on mode hint information, the mode hint information based on task metric information and a user interaction determination, wherein at least one of a frequency and a voltage for at least the one or more first cores is to be updated based on the updated power management policy; and

a system memory coupled to the processor, wherein the system memory comprises a hardware feedback data structure to store the first and second hardware feedback information.

19. The system of claim 18 , wherein the first hardware feedback information comprises performance information and the second hardware feedback information comprises energy efficiency information.

20. The system of claim 18 , further comprising a scheduler to update a background task affinity structure based at least in part on the first and second hardware feedback information and use the updated background task affinity structure to schedule one or more background tasks to the one or more first cores.

Assignees

• Intel Corp

Inventors

• Zhu Jianfang
• Kirubakaran Deepak Samuel
• Rivas Toledano Raoul
• Nge Chee Lim
• Chabukswar Rajshree
• Hermerding Ii James
• Nair Sudheer
• Braun William
• Wang Zhongsheng
• Fenger Russell
• Kapaley Udayan

Classifications

• G06F9/4893 Primary

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/329 Primary

  by task scheduling · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title