System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment

Patent metadata

Field	Value
Publication number	US-11770349-B2
Application number	US-201715415497-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Jan 27, 2016
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. A mapping table in DRAM can be provided through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

First claim

What is claimed is:

1. A system for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, comprising:
one or more microprocessors;
at least one subnet, the at least one subnet comprising:
a plurality of switches, the plurality of switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports,
a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port,
a plurality of end nodes, wherein each of the plurality of end nodes access the at least one subnet via at least one host channel adapter of the plurality of host channel adapters, and
a plurality of hardware-based P_Key tables, each of the plurality of hardware-based P_Key tables being provided at a respective switch of the plurality of switches;

wherein each of the plurality of end nodes assigned to at least one of a plurality of partitions;
wherein each of the plurality of partitions are defined by a P_Key value of a plurality of P_Key values;
wherein a switch port of a switch of the plurality of switches accesses a hardware-based P_Key bitmap of the switch, wherein the hardware-based P_Key bitmap comprises a bitmap comprising a plurality of bits, wherein each bit corresponds to a P_Key of the plurality of P_Key values;
wherein the hardware-based P_Key bitmap is associated with a virtual P_Key table stored within both a memory of the switch and a memory external to the switch and a subnet manager, the virtual P_Key table being stored within the memory of the switch and the external memory by a subnet management agent of the switch, wherein the virtual P_Key table provides a legacy representation of the hardware-based P_Key table to the subnet manager, a version of the software the subnet manager is running not comprising a definition that supports interaction and query of a hardware-based P_Key bitmap by the subnet manager, wherein the memory external to the switch is accessible by the subnet manager; and
wherein upon the subnet manager writing a new P_Key value to the virtual P_Key table at the memory external to the switch, the subnet management agent updates the hardware-based P_Key bitmap via a hardware access layer, the update of the hardware-based P_Key bitmap reflecting the new P_Key value written to the virtual P_Key table by the subnet manager.

2. The system of claim 1 ,
wherein the subnet manager determines allowed and disallowed traffic through the plurality of ports on each of the plurality of switches.

3. The system of claim 2 ,
wherein the subnet manager configures, via the associated virtual P_Key table, the hardware-based P_Key bitmap based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the plurality of switches.

4. The system of claim 3 , wherein the virtual P_Key table is limited in size based upon an amount of memory at the switch comprising the switch port associated with the hardware-based P_Key table.

5. The system of claim 3 , wherein the virtual P_Key table is hosted on memory external from the switch comprising the switch port associated with the hardware-based P_Key table.

6. The system of claim 1 , wherein the systems comprises two or more subnets, each of the two or more subnets being interconnected by at least one router port in each of the two or more subnets.

7. A method for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, comprising:
providing, at one or more computers, including one or more microprocessors,
at least one subnet, the at least one subnet comprising:
a plurality of switches, the plurality of switches comprising at least a leaf switch, wherein each of the plurality of switches comprise a plurality of switch ports,
a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port,
a plurality of end nodes, wherein each of the end nodes access the at least one subnet via at least one host channel adapter of the plurality of host channel adapters, and
a plurality of hardware-based P_Key tables, each of the plurality of hardware-based P_Key tables being provided at a respective switch of the plurality of switches;

assigning, by the subnet manager, each of the plurality of end nodes to at least one of a plurality of partitions, wherein each of the plurality of partitions are defined by a P_Key value of a plurality of P_Key values;
accessing, by a switch port of a switch of the plurality of switches, a hardware-based P_Key bitmap of the switch, wherein the hardware-based P_Key bitmap comprises a bitmap comprising a plurality of bits, wherein each bit corresponds to a P_Key of the plurality of P_Key values;
associating the hardware-based P_Key bitmap with a virtual P_Key table stored within both a memory of the switch and a memory external to the switch and a subnet manager, the virtual P_Key table being stored within the memory of the switch and the external memory by a subnet management agent of the switch, wherein the virtual P_Key table provides a legacy representation of the hardware-based P_Key table to the subnet manager, a version of the software the subnet manager is running not comprising a definition that supports interaction and query of a hardware-based P_Key bitmap by the subnet manager; and
upon the subnet manager writing a new P_Key value to the virtual P_Key table at the memory external to the switch, updating, by the subnet management agent, via a hardware access layer, the hardware-based P_Key bitmap, the update of the hardware-based P_Key bitmap reflecting the new P_Key value written to the virtual P_Key table by the subnet manager.

8. The method of claim 7 , further comprising:
determining, by the subnet manager, allowed and disallowed traffic through the plurality of ports on each of the plurality of switches.

9. The method of claim 8 further comprising:
configuring, by the subnet manager via the associated virtual P_Key table, the hardware-based P_Key bitmap based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the plurality of switches.

10. The method of claim 9 , wherein the virtual P_Key table is limited in size based upon an amount of memory at the switch comprising the switch port associated with the hardware-based P_Key table.

11. The method of claim 9 , wherein the virtual P_Key table is hosted on memory external from the switch comprising the switch port associated with the hardware-based P_Key table.

12. The method of claim 7 , wherein the at least one subnet comprise two or more subnets, each of the two or more subnets being interconnected by at least one router in each of the two or more subnets.

13. A non-transitory computer readable storage medium, including instructions stored thereon for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, which when read and executed by one or more computers cause the one or more computers to perform steps comprising:
providing, at one or more computers, including one or more microprocessors,
at least one subnet, the at least one subnet comprising:
a plurality of switches, the plurality of switches comprising at least a leaf switch, wherein each of the plurality of switches comprise a plurality of switch ports,
a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port,
a plurality of end nodes, wher

Assignees

• Oracle Int Corp

Inventors

• Johnsen Bjørn Dag
• Narasimhamurthy Prabhunandan
• Holen Line

Classifications

• H04L45/02

  Topology update or discovery · CPC title

• H04L41/12

  Discovery or management of network topologies · CPC title

• H04L45/48

  Routing tree calculation · CPC title

• H04L49/118

  Address processing within a device, e.g. using internal ID or tags for routing within a switch · CPC title

• H04L49/111

  Switch interfaces, e.g. port details · CPC title