Mixed-signal dot product processor with single capacitor per multiplier

Patent metadata

Field	Value
Publication number	US-11770130-B2
Application number	US-202016808708-A
Country	US
Kind code	B2
Filing date	Mar 4, 2020
Priority date	Mar 4, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.

First claim

What is claimed is:

1. A mixed-signal logic processor, comprising:
a dot product computation portion having a plurality of mixed-signal multiplier branches, each of the plurality of mixed-signal multiplier branches connected to a single common node, and each of the plurality of mixed-signal multiplier branches having a set of branch-dedicated switches and a single branch-dedicated capacitor where each branch has a different voltage level, the set including two switches connected in parallel, wherein the dot product computation portion further includes:
a common switch being external to each of the plurality of mixed-signal multiplier branches; and
a first shared branch-external capacitor and a second shared branch-external capacitor positioned directly on opposed ends of the common switch without any other electrical connections therebetween, the first and the second shared branch-external capacitors being external to each of the plurality of mixed-signal multiplier branches such that only the first shared branch-external capacitor directly connects to the single common node connecting all of the plurality of mixed-signal multiplier branches,

wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor comprising a reset mode, a sample mode, a merge mode, and an accumulate mode for a dot product computation.

2. The mixed-signal logic processor of claim 1 , wherein the first shared branch-external capacitor and the second shared branch-external capacitor are parallel to each other.

3. The mixed-signal logic processor of claim 1 , wherein the mixed-signal logic processor is configured to compute a dot product between an analog value vector and a digital value vector.

4. The mixed-signal logic processor of claim 3 , wherein the mixed-signal logic processor is comprised in a system having at least one sensor and a memory device, wherein the analog value vector is received from the at least one sensor and the digital value vector is received from the memory device.

5. The mixed-signal logic processor of claim 3 , wherein an inner product of the mixed-signal logic processor is given as:
{right arrow over (x)}·{right arrow over (w)}=x 1 w 1 +x 2 w 2 + . . . +x N w N ,
where {right arrow over (x)}=[x 1 x 2 . . . x N ], {right arrow over (w)}=[w 1 w 2 . . . w N ], x n s are analog inputs, and w n s represents B-bit digital values, that is:
w n =w n,0 +2 w n,1 + . . . +2 B−1 w n,B−1 ,

where w n,b ∈{0,1}: n-th element's b-th bit.

6. The mixed-signal logic processor of claim 1 , wherein the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches is of a same size.

7. The mixed-signal logic processor of claim 1 , wherein the set of branch-dedicated switches include a first switch and a second switch, each having a first side connected to one side of the single branch-dedicated capacitor, wherein another side of the first switch is connected to an input voltage, and the another side of the second switch bypasses the input voltage.

8. The mixed-signal logic processor of claim 7 , wherein the set of branch-dedicated switches include a third switch having a first side connected to the one side of the branch-dedicated capacitor and a second side connected to a common node with respect to each of the plurality of mixed-signal multiplier branches.

9. The mixed-signal logic processor of claim 1 , wherein capacitor-wise each of the plurality of mixed-signal multiplier branches include only the single branch-dedicated capacitor.

10. The mixed-signal logic processor of claim 1 , wherein the various modes of the mixed-signal logic processor comprise a reset mode, a sample mode, a merge mode, and an accumulate mode.

11. A method for forming a mixed-signal logic processor, comprising:
forming a dot product computation portion by arranging a plurality of mixed-signal multiplier branches to each have a set of branch-dedicated switches and a single branch-dedicated capacitor, each of the plurality of mixed-signal multiplier branches connected to a single common node and each branch having a different voltage level, and the set comprising two switches connected in parallel, wherein the dot product computation portion further comprises:
connecting a common switch external to each of the plurality of mixed-signal multiplier branches; and
positioning the common switch between a first shared branch-external capacitor and a second shared branch-external capacitor such that only the first shared branch-external capacitor directly connects to the common single node connecting all of the plurality of mixed-signal multiplier branches;

wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor comprising a reset mode, a sample mode, a merge mode, and an accumulate mode for a dot product computation.

12. The method of claim 11 , wherein the first shared branch-external capacitor and the second shared branch-external capacitor are parallel to each other.

13. The method of claim 11 , further comprising configuring the mixed-signal logic processor to compute a dot product between an analog value vector and a digital value vector.

14. The method of claim 13 , wherein the mixed-signal logic processor is comprised in a system having at least one sensor and a memory device, and wherein the method further comprising receiving the analog value vector from the at least one sensor and receiving the digital value vector from the memory device.

15. The method of claim 13 , further comprising configuring the sample mode to sample the analog value vector using the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches to store a sample value.

16. The method of claim 11 , wherein an inner product of the mixed-signal logic processor is given as:
{right arrow over (x)}·{right arrow over (w)}=x 1 w 1 +x 2 w 2 + . . . +x N w N ,
where {right arrow over (x)}=[x 1 x 2 . . . x N ], {right arrow over (w)}=[w 1 w 2 . . . w N ], x n s are analog inputs, and w n s represents B-bit digital values, that is:
w n =w n,0 +2 w n,1 + . . . +2 B−1 w n,B−1 ,

where w n,b ∈{0,1}: n-th element's b-th bit.

17. The method of claim 11 , wherein the set of branch-dedicated switches include a first switch and a second switch, and the method further comprises:
connecting a first side of the first switch and the second switch to one side of the single branch-dedicated capacitor;
connecting a second side of the first switch is connected to an input voltage; and
bypassing the input voltage by a seconds side of the second switch.

18. A computer processing system, comprising:
a mixed-signal logic processor, wherein the mixed-signal logic processor comprises:
a dot product computation portion having a plurality of mixed-signal multiplier branches, each of the plurality of mixed-signal multiplier branches connected to a single common node, and each of the plurality of mixed-signal multiplier branches having a set of branch-dedicated switches and a single branch-dedicated capacitor where each branch has a different voltage level, the set including two switches connected in parallel, wherein the dot product computation portion further comprises:
a common switch being external to each of the plurality of mixed-signal multiplier branches; and
a first shared branch-external capacitor and a second shared branch-external capacitor pos

Assignees

• IBM

Inventors

• Kang Mingu
• Kim Seyoung
• Woo Seonghoon

Classifications

• H03M1/466 Primary

  using switched capacitors · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06N3/065

  Analogue means · CPC title