Pipelined analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-11770129-B2
Application number	US-202117484581-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

First claim

What is claimed is:

1. An apparatus comprising:
a pipelined analog-to-digital converter comprising:
a first stage comprising:
a sampler;
a quantizer comprising a time-to-digital converter (TDC), the quantizer coupled to the sampler;
a current distribution circuit coupled to the sampler; and
a comparator coupled between the sampler and the quantizer and between the sampler and the current distribution circuit; and

a second stage comprising:
a sampler coupled to the current distribution circuit; and
a quantizer coupled to the sampler of the second stage.

2. The apparatus of claim 1 , wherein:
the second stage comprises a comparator;
the comparator of the second stage is coupled between the sampler of the second stage and the quantizer of the second stage; and
the quantizer of the second stage comprises successive approximation register (SAR) logic.

3. The apparatus of claim 2 , wherein:
the sampler of the second stage comprises:
multiple capacitors; and
multiple switches, each respective switch of the multiple switches coupled in series with a respective capacitor of the multiple capacitors; and

the successive approximation register (SAR) logic is configured to set respective states of respective switches of the multiple switches based on an output of the comparator of the second stage.

4. The apparatus of claim 3 , wherein:
each respective capacitor of the multiple capacitors comprises a first plate and a second plate;
each respective switch of the multiple switches is coupled to the second plate of the respective capacitor of the multiple capacitors; and
the current distribution circuit is coupled to the first plate of each respective capacitor of the multiple capacitors.

5. The apparatus of claim 1 , further comprising:
at least one switch coupled between an input of the first stage and the sampler of the first stage; and
one or more switches coupled between the current distribution circuit and the sampler of the first stage and the sampler of the second stage.

6. The apparatus of claim 1 , wherein the current distribution circuit is configured to:
apply at least one current to the sampler of the first stage and the sampler of the second stage.

7. The apparatus of claim 6 , wherein the current distribution circuit is configured to:
discharge the sampler of the first stage and charge the sampler of the second stage by applying the at least one current respectively to the sampler of the first stage and to the sampler of the second stage.

8. The apparatus of claim 7 , wherein the current distribution circuit is configured to:
charge the sampler of the second stage at least partially while discharging the sampler of the first stage.

9. The apparatus of claim 6 , wherein:
the current distribution circuit comprises at least one current source; and
the at least one current source is configured to apply the at least one current by routing a same current to the sampler of the first stage and the sampler of the second stage.

10. The apparatus of claim 6 , wherein:
the current distribution circuit comprises a first current source and a second current source, the first and second current sources arranged into a current mirror;
the current mirror is configured to provide a first current and a second current; and
the current mirror is configured to apply the at least one current by routing the first current to the sampler of the first stage and the second current to the sampler of the second stage.

11. The apparatus of claim 6 , wherein:
the current distribution circuit comprises a first current source and a second current source;
the first current source is configured to provide a first current;
the second current source is configured to provide a second current, the second current having a lower magnitude than the first current; and
the current distribution circuit is configured to apply the at least one current by applying the first current before the second current.

12. The apparatus of claim 1 , wherein:
the comparator is configured to control application of at least one current by the current distribution circuit.

13. The apparatus of claim 12 , wherein:
the quantizer is configured to determine a digital value based on an output of the comparator.

14. The apparatus of claim 13 , wherein the current distribution circuit is configured to:
provide, using the at least one current, analog information to the sampler of the second stage at least partially while the quantizer of the first stage is determining the digital value, the analog information related to an analog signal sampled by the sampler of the first stage.

15. The apparatus of claim 13 , wherein:
the time-to-digital converter (TDC) is configured to convert a time period that is indicated by the comparator to the digital value.

16. The apparatus of claim 1 , wherein the pipelined analog-to-digital converter comprises:
a residue determiner coupled to the current distribution circuit and the quantizer of the first stage, wherein:
the current distribution circuit is configured to apply at least one current to the residue determiner; and
the quantizer of the first stage is configured to:
generate a digital value; and
provide the digital value to the residue determiner.

17. The apparatus of claim 16 , wherein:
the quantizer of the first stage is configured to couple bits of the digital value to the residue determiner as the bits of the digital value are being generated.

18. The apparatus of claim 1 , wherein the pipelined analog-to-digital converter comprises:
a third stage comprising:
a sampler;
a quantizer coupled to the sampler of the third stage; and
a current distribution circuit coupled to the sampler of the third stage and the sampler of the first stage,

wherein the current distribution circuit of the third stage is configured to apply at least one current to the sampler of the third stage and the sampler of the first stage.

19. The apparatus of claim 18 , wherein:
the current distribution circuit of the third stage is configured to provide, using the at least one current, first analog information to the sampler of the first stage at least partially while the quantizer of the third stage is determining a first digital value, the first analog information related to an analog signal sampled by the sampler of the third stage; and
the current distribution circuit of the first stage is configured to provide, using at least one other current, second analog information to the sampler of the second stage at least partially while the quantizer of the first stage is determining a second digital value, the second analog information related to the first analog information provided to the sampler of the first stage by the current distribution circuit of the third stage.

20. The apparatus of claim 1 , further comprising:
a wireless interface device,
wherein the wireless interface device comprises the pipelined analog-to-digital converter.

21. The apparatus of claim 20 , further comprising:
a display screen; and
at least one processor operatively coupled to the display screen and at least a portion of the wireless interface device, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals received using the pipelined analog-to-digital converter of the wireless interface device.

22. An apparatus for pipelined analog-to-digital conversion, the apparatus compr

Assignees

• Qualcomm Inc

Inventors

• Mirhaj Seyed Arash
• Sun Lei
• Guo Yuhua
• Dagher Elias
• Akhavan Aram
• Wang Yan
• Alladi Dinesh Jagannath

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/54

  Input signal sampled and held with linear return to datum · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/167 Primary

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H03M1/164 Primary

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title