Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11769747-B2
Application number	US-202117350473-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Dec 16, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first insulator;
a first pad provided in the first insulator, and including:
a first layer provided on a lateral face and a lower face of the first insulator, and
a second layer provided on the lateral face and the lower face of the first insulator via the first layer;

a second insulator provided on the first insulator;
a second pad provided on the first pad in the second insulator, and including:
a third layer provided on a lateral face and an upper face of the second insulator, and
a fourth layer provided on the lateral face and the upper face of the second insulator via the third layer; and

a metal layer provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element and oxygen, the metal element being the same as a metal element included in the first layer or the third layer.

2. The device of claim 1 , wherein the metal element includes titanium, aluminum, or manganese.

3. The device of claim 1 , wherein
the first layer is in contact with the lateral face and the lower face of the first insulator, or
the third layer is in contact with the lateral face and the upper face of the second insulator.

4. The device of claim 1 , wherein
the first insulator includes a first film including oxygen and being in contact with a lower face of the metal layer, or
the second insulator includes a second film including oxygen and being in contact with an upper face of the metal layer.

5. The device of claim 4 , wherein the first film or the second film is a native oxidized film.

6. The device of claim 4 , wherein
the first insulator includes:
the first film, and
a third film including carbon and nitrogen and being in contact with a lower face of the first film, or

the second insulator includes:
the second film, and
a fourth film including carbon and nitrogen and being in contact with an upper face of the second film.

7. The device of claim 1 , wherein the first pad and the second pad have same widths.

8. The device of claim 1 , wherein the first pad and the second pad have different widths.

9. The device of claim 1 , wherein
the first pad is provided on a first plug including the first and second layers, and the second layer in the first plug is in contact with the second layer in the first pad, or
the second pad is provided below a second plug including the third and fourth layers, and the fourth layer in the second plug is in contact with the fourth layer in the second pad.

10. A semiconductor device comprising:
a first insulator;
a first pad provided in the first insulator, and including:
a first layer provided on a lateral face and a lower face of the first insulator, and
a second layer provided on the lateral face and the lower face of the first insulator via the first layer;

a second insulator provided on the first insulator;
a second pad provided at a position where the second pad is not in contact with the first pad in the second insulator, and including:
a third layer provided on a lateral face and an upper face of the second insulator, and
a fourth layer provided on the lateral face and the upper face of the second insulator via the third layer; and

a metal layer provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element and oxygen, the metal element being the same as a metal element included in the first layer or the third layer.

11. The device of claim 10 , wherein the metal element includes titanium, aluminum, or manganese.

12. The device of claim 10 , wherein
the first layer is in contact with the lateral face and the lower face of the first insulator, or
the third layer is in contact with the lateral face and the upper face of the second insulator.

13. The device of claim 10 , wherein
the first insulator includes a first film including oxygen and being in contact with a lower face of the metal layer, or
the second insulator includes a second film including oxygen and being in contact with an upper face of the metal layer.

14. The device of claim 13 , wherein
the first insulator includes:
the first film, and
a third film including carbon and nitrogen and being in contact with a lower face of the first film, or

the second insulator includes:
the second film, and
a fourth film including carbon and nitrogen and being in contact with an upper face of the second film.

Assignees

• Kioxia Corp

Inventors

• Sawada Genki
• Tagami Masayoshi
• Iijima Jun
• Kume Ippei
• Yoshida Kiyomitsu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title