Chip structure, packaging structure and manufacturing method for chip structure

Patent metadata

Field	Value
Publication number	US-11769745-B2
Application number	US-202117489759-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Oct 30, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board.

First claim

What is claimed is:

1. A chip structure, comprising at least one chip body, each of which comprises at least one radio frequency front-end device,
wherein the chip structure further comprises a redistribution layer stacked on the at least one chip body and at least one pin on the redistribution layer; and
each of the at least one radio frequency front-end device at least corresponds to one pin of the at least one pin; the pin is electrically connected to the corresponding radio frequency front-end device through a corresponding electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device on a surface of the redistribution layer is consistent with an extending direction of the pin corresponding to the radio frequency front-end device on the surface of the redistribution layer, and a surface of the pin distal to the redistribution layer is a first plane; and
wherein the chip structure further comprises at least one via corresponding to the at least one pin in the redistribution layer, wherein the electrical connector is arranged in the corresponding via, comprises a first conductive connection layer, a second conductive connection layer and a conductive connection body sequentially arranged along a direction distal to the radio frequency front-end device; and the conductive connection body is configured to be connected to the pin, and
the first conductive connection layer covers a side wall and a bottom wall of the via and is electrically connected to the radio frequency front-end device; the second conductive connection layer covers the first conductive connection layer and has a recess in the redistribution layer as a secondary via; and the conductive connection body is in the secondary via, and is electrically connected to the pin.

2. The chip structure according to claim 1 , wherein the first plane has a shape of a first rectangle, and a surface of the radio frequency front-end device proximal to the pin has a shape of a second rectangle.

3. The chip structure according to claim 2 , wherein a size of the first rectangle and/or the second rectangle is within 2 mm×50 mm.

4. The chip structure according to claim 1 , wherein the redistribution layer is a passivation layer.

5. The chip structure according to claim 1 , wherein
a portion of the at least one chip body comprises a radio frequency inlet region, a radio frequency outlet region and a power supply region; and
the radio frequency inlet region, the radio frequency outlet region and the power supply region have one or more radio frequency front-end devices, respectively.

6. The chip structure according to claim 5 , wherein a surface of the chip body in contact with the redistribution layer is a rectangle; the radio frequency inlet region comprises a plurality of sub-inlet regions symmetrically arranged on two opposite sides of the rectangle, and each of the plurality of sub-inlet region has one radio frequency front-end device; the radio frequency outlet region comprises a plurality of sub-outlet regions symmetrically arranged on two opposite sides of the rectangle, and each of the plurality of sub-outlet regions has one radio frequency front-end device; the power region comprises a plurality of sub-power regions symmetrically arranged on two opposite sides of the rectangle, and each of the plurality of sub-power regions has one radio frequency front-end device.

7. The chip structure according to claim 1 , wherein the pin, the conductive connection body and the second conductive connection layer are made of a same material.

8. The chip structure according to claim 7 , wherein the pin, the conductive connection body and the second conductive connection layer are all made of gold; and
the first conductive connection layer comprises a titanium metal layer and/or a tungsten metal layer.

9. A packaging structure, comprising a flexible circuit board and the chip structure according to claim 1 ,
wherein the flexible circuit board comprises at least one electrical connection pad electrically connected to the at least one pin.

10. The packaging structure according to claim 9 , wherein the first plane has a shape of a first rectangle, and a surface of the radio frequency front-end device proximal to the pin has a shape of a second rectangle.

11. The packaging structure according to claim 10 , wherein a size of the first rectangle and/or the second rectangle is within 2 mm×50 mm.

12. The packaging structure according to claim 9 , wherein the redistribution layer is a passivation layer.

13. A manufacturing method for a chip structure, comprising steps of:
providing at least one chip body such that the at least one chip body comprises at least one radio frequency front-end device;
forming a redistribution layer on the at least one chip body;
forming at least one pin on the redistribution layer such that each of the at least one pin is electrically connected to a corresponding radio frequency front-end device through a corresponding electrical connector extending through the redistribution layer, and each of the at least one radio frequency front-end device at least corresponds to one pin of the at least one pin, wherein an extending direction of the pin on a surface of the redistribution layer is consistent with an extending direction of the radio frequency front-end device corresponding to the pin on the surface of the redistribution layer; and a surface of the pin distal to the redistribution layer is a first plane,
wherein the step of forming at least one pin on the redistribution layer such that each of the at least one pin is electrically connected to a corresponding radio frequency front-end device through a corresponding electrical connector extending through the redistribution layer comprises steps of:
forming a via extending through the redistribution layer at a position where the redistribution layer covers the radio frequency front-end device;
forming a first conductive connection layer of the electrical connector such that the first conductive connection layer covers a side wall and a bottom wall of the via and is electrically connected to the radio frequency front-end device;
forming a second conductive connection layer of the electrical connector on the first conductive connection layer such that a recess is formed in the redistribution layer as a secondary via;
coating photoresist on the second conductive connection layer, and performing an exposure process and a development process on the photoresist, to form a molding cavity of the pin and expose the secondary via;
forming a conductive connection body of the electrical connector within the secondary via, and forming the pin within the molding cavity; and
removing a portion of the first conductive connection layer and the second conductive connection layer which are not covered by the pin.

14. The manufacturing method according to claim 13 , wherein the step of forming the first conductive connection layer of the electrical connector comprises forming the first conductive connection layer of the electrical connector through a magnetron sputtering process; and
the step of forming the second conductive connection layer of the electrical connector on the first conductive connection layer comprises forming the second conductive connection layer of the electrical connector on the first conductive connection layer through a magnetron sputtering process.

15. The manufacturing method according to claim 14 , wherein
the step of forming the conductive connection body of the electrical connector within the secondary via and forming the pin wi

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Zongmin
• Duan Liye
• Huang Jijing
• Hou Mengjun

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title