Non-volatile memory devices and systems with read-only memory features and methods for operating the same

Patent metadata

Field	Value
Publication number	US-11769561-B2
Application number	US-202017119509-A
Country	US
Kind code	B2
Filing date	Dec 11, 2020
Priority date	Apr 23, 2018
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

First claim

What is claimed is:

1. A method of operating a memory device including a non-volatile memory array, comprising:
sending a command to the memory device to configure a subset of the non-volatile memory array to not implement erase or write commands; and
storing data configured to be read-only in the subset of the non-volatile memory array,
wherein sending the command to the memory device comprises instructing the memory device to store one or more addresses corresponding to the subset in a write-once read-many (WORM) memory of the memory device.

2. The method of claim 1 , wherein the write-once read-many (WORM) memory comprises an array of fuses, anti-fuses, or a combination thereof.

3. The method of claim 1 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

4. The method of claim 1 , wherein storing the data configured to be read-only in the subset of the non-volatile memory array comprises sending a write command targeting the subset of the non-volatile memory array to the memory device.

5. The method of claim 1 , wherein storing the data is performed before sending the command.

6. The method of claim 1 , wherein configuring the subset to not implement write commands includes configuring the subset to not implement overwrite commands.

7. A method of operating a memory device including a non-volatile memory array, comprising:
configuring a subset of the non-volatile array of the memory device to not implement erase or write commands; and
storing data configured to be read-only in the subset of the non-volatile memory array,
wherein configuring the subset comprises storing one or more addresses corresponding to the subset in a write-once read-many (WORM) memory of the memory device.

8. The method of claim 7 , wherein the write-once read-many (WORM) memory comprises an array of fuses, anti-fuses, or a combination thereof.

9. The method of claim 7 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

10. The method of claim 7 , wherein storing the data configured to be read-only in the subset of the non-volatile memory array comprises sending a write command targeting the subset of the non-volatile memory array to the memory device.

11. The method of claim 7 , wherein storing the data is performed after configuring the subset.

12. The method of claim 7 , wherein configuring the subset to not implement write commands includes configuring the subset to not implement overwrite commands.

13. A method of operating a memory device including a non-volatile memory array, comprising:
configuring a subset of the non-volatile array of the memory device as a write-one, read-many (WORM) memory; and
storing data configured to be read-only in the subset of the non-volatile memory array.

14. The method of claim 13 , wherein configuring the subset comprises storing one or more addresses corresponding to the subset in a mode register or fuse array of the memory device.

15. The method of claim 13 , wherein storing the data is performed after configuring the subset.

16. The method of claim 13 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

Assignees

• Micron Technology Inc

Inventors

• Cowles Timothy B
• Raad George B
• Rehmeyer James S
• Parry Jonathan S

Classifications

• G11C17/08 Primary

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/1695

  Protection circuits or methods · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title

• G11C11/2295

  Protection circuits or methods · CPC title