Signal generating circuit and method, and semiconductor memory

Patent metadata

Field	Value
Publication number	US-11769536-B2
Application number	US-202217651475-A
Country	US
Kind code	B2
Filing date	Feb 17, 2022
Priority date	Jul 2, 2021
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.

First claim

What is claimed is:

1. A signal generating circuit, comprising:
a clock circuit, configured to receive an external clock signal to generate an internal clock signal;
a controlling circuit, configured to generate a control signal according to a frequency of the external clock signal; and
a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal; wherein when the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level;
wherein the generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.

2. The signal generating circuit of claim 1 , wherein the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

3. The signal generating circuit of claim 1 , wherein the generating circuit comprises a counter; and wherein when the flag signal changes from the first level to the second level, the counter starts to count the internal clock signal, and after a count value of the counter reaches a target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

4. The signal generating circuit of claim 1 , wherein the frequency of the external clock signal does not change with variations in temperature and process.

5. The signal generating circuit of claim 1 , wherein the flag signal is a check flag signal, and wherein the check flag signal is used to represent a parity check error or a redundancy check error.

6. The signal generating circuit of claim 1 , wherein the clock circuit is specifically configured to shield the external clock signal based on the flag signal to generate the internal clock signal.

7. The signal generating circuit of claim 6 , wherein the clock circuit comprises a logic AND gate; and
wherein the logic AND gate is configured to receive the flag signal and the external clock signal to generate the internal clock signal.

8. The signal generating circuit of claim 1 , wherein
the target value represented by the control signal increases with increasing of the frequency of the external clock signal.

9. The signal generating circuit of claim 1 , wherein the controlling circuit comprises a mode register and a calculator; wherein
the mode register is configured to store a delay tCCD between adjacent column address strobe signals, and output a first code to represent the delay tCCD between the adjacent column address strobe signals; and
the calculator is configured to receive the first code, and multiply the first code by a coefficient to output as the control signal.

10. A semiconductor memory, comprising the signal generating circuit of claim 1 .

11. The semiconductor memory of claim 10 , wherein the semiconductor memory is a Dynamic Random Access Memory (DRAM) chip, and a memory of the DRAM chip complies with specifications of DDR4.

12. A signal generating method, comprising:
receiving, by a clock circuit, an external clock signal to generate an internal clock signal, and outputting the internal clock signal to a generating circuit;
generating, by a controlling circuit, a control signal according to a frequency of the external clock signal, and outputting the control signal to the generating circuit; and
receiving, by the generating circuit, the internal clock signal, the control signal and a flag signal to generate a target signal; when the flag signal changes from a first level to a second level, controlling the target signal to change from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, controlling the target signal to change from the fourth level to the third level; wherein the target time length is determined by the generating circuit according to the internal clock signal and the control signal.

13. The signal generating method of claim 12 , wherein the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

14. The signal generating method of claim 12 , wherein the when the flag signal changes from the first level to the second level, controlling the target signal to change from the third level to the fourth level, and after the target signal maintains the fourth level for the target time length, controlling the target signal to change from the fourth level to the third level, comprises:
when the flag signal changes from the first level to the second level, controlling, by a counter comprised in the generating circuit, the internal clock signal, and after a count value of the counter reaches a target value represented by the control signal, controlling, by the counter, the target signal to change from the fourth level to the third level.

15. The signal generating method of claim 12 , wherein the frequency of the external clock signal does not change with variation of temperature and process.

16. The signal generating method of claim 12 , wherein the flag signal is a check flag signal, and wherein the check flag signal is used to represent a parity check error or a redundancy check error.

17. The signal generating method of claim 12 , wherein receiving, by the clock circuit, the external clock signal to generate the internal clock signal comprises:
shielding, by the clock circuit, the external clock signal based on the flag signal to generate the internal clock signal.

18. The signal generating method of claim 17 , wherein receiving, by the clock circuit, the external clock signal to generate the internal clock signal comprises:
receiving, by a logic AND gate comprised in the clock circuit, the flag signal and the external clock signal to generate the internal clock signal.

19. The signal generating method of claim 12 , wherein
the target value represented by the control signal increases with increasing of the frequency of the external clock signal.

20. The signal generating method of claim 12 , wherein generating, by the controlling circuit, the control signal according to the frequency of the external clock signal comprises:
outputting, by a mode register comprised in the controlling circuit, a first code to represent a delay tCCD between adjacent column address strobe signals, wherein the mode register stores the delay tCCD; and
receiving, by a calculator comprised in the controlling circuit, the first code, and multiplying the first code by a coefficient to output as the control signal.

Assignees

• Changxin Memory Tech Inc

Inventors

• Huang Zequn

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03K5/151

  with two complementary outputs · CPC title