Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Patent metadata

Field	Value
Publication number	US-11769288-B2
Application number	US-202217868618-A
Country	US
Kind code	B2
Filing date	Jul 19, 2022
Priority date	Dec 28, 2018
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

First claim

What is claimed is:

1. An apparatus comprising:
a scheduling circuit to dispatch a single batch on an execution circuit responsive to a particular triggering event, the single batch including multiple aggregated shader invocations, the multiple aggregated shader invocations being aggregated from a ray traversal thread traversing a single ray through a plurality of hierarchically arranged nodes and intersecting the single ray with a primitive contained within at least one of the plurality of hierarchically arranged nodes; and
the execution circuit to execute the single dispatched batch.

2. The apparatus of claim 1 , wherein the particular triggering event comprises determination of a workload on the execution circuit warranting to dispatch the single batch.

3. The apparatus of claim 1 , wherein the ray traversal thread is to be suspended pending execution results of the single batch execution, wherein a first traversal context of the ray traversal thread is to be maintained while the ray traversal thread is suspended.

4. The apparatus of claim 1 , further comprising:
a ray tracing circuit to execute the ray traversal thread traversing the single ray through the plurality of hierarchically arranged nodes.

5. The apparatus of claim 1 , wherein the multiple aggregated shader invocations are associated with a same traversal context.

6. The apparatus of claim 1 , further comprising:
circuitry to regroup data associated with the single batch to increase occupancy for operations performed by the execution circuit.

7. The apparatus of claim 1 , wherein accumulating the multiple aggregated shader invocations comprises storing a data entry in a data structure in a memory, the data structure comprising at least one entry for each shader, each entry usable to identify shader information required to execute a corresponding shader.

8. The apparatus of claim 1 , wherein the particular triggering event comprises a particular temporal event or processing event.

9. A method comprising:
dispatching a single batch on an execution circuit responsive to a particular triggering event, the single batch including multiple aggregated shader invocations, the multiple aggregated shader invocations being aggregated from a ray traversal thread traversing a single ray through a plurality of hierarchically arranged nodes and intersecting the single ray with a primitive contained within at least one of the plurality of hierarchically arranged nodes; and
executing the single dispatched batch.

10. The method of claim 9 , wherein the particular triggering event comprises determination of a workload on the execution circuit warranting to dispatch the single batch.

11. The method of claim 9 , wherein the ray traversal thread is to be suspended pending execution results of the single batch execution, wherein a first traversal context of the ray traversal thread is to be maintained while the ray traversal thread is suspended.

12. The method of claim 10 , further comprising:
executing the ray traversal thread traversing the single ray through the plurality of hierarchically arranged nodes.

13. The method of claim 9 , wherein the multiple aggregated shader invocations are associated with a same traversal context.

14. The method of claim 9 , further comprising:
regrouping data associated with the single batch to increase occupancy for operations performed in executing the single dispatched batch.

15. The method of claim 9 , wherein accumulating the multiple aggregated shader invocations comprises storing a data entry in a data structure in a memory, the data structure comprising at least one entry for each shader, each entry usable to identify shader information required to execute a corresponding shader.

16. The method of claim 9 , wherein the particular triggering event comprises a particular temporal event or processing event.

17. A non-transitory computer readable medium that stores instructions, which when executed by a processor, causing the processor to perform:
dispatching a single batch on an execution circuit responsive to a particular triggering event, the single batch including multiple aggregated shader invocations, the multiple aggregated shader invocations being aggregated from a ray traversal thread traversing a single ray through a plurality of hierarchically arranged nodes and intersecting the single ray with a primitive contained within at least one of the plurality of hierarchically arranged nodes; and
executing the single dispatched batch.

18. The non-transitory computer readable medium of claim 17 , wherein the particular triggering event comprises determination of a workload on the execution circuit warranting to dispatch the single batch.

19. The non-transitory computer readable medium of claim 17 , wherein the ray traversal thread is to be suspended pending execution results of the single batch execution, wherein a first traversal context of the ray traversal thread is to be maintained while the ray traversal thread is suspended.

20. The non-transitory computer readable medium of claim 17 , wherein the multiple aggregated shader invocations are associated with a same traversal context.

Assignees

• Intel Corp

Inventors

• Liktor Gabor
• Vaidyanathan Karthik
• Amstutz Jefferson
• Kuwahara Atsuo
• Doyle Michael
• Schluessler Travis

Classifications

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T2210/21

  Collision detection, intersection · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title