Thin-film transistor (TFT) architecture for liquid crystal displays

Patent metadata

Field	Value
Publication number	US-11768408-B2
Application number	US-201816632814-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Jul 21, 2017
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A device having a stack of layers defining source and pixel conductors at a first level, gate and common conductors at a second level, semiconductor channels between the source and pixel conductors and gate dielectric capacitively coupling the semiconductor channels to the gate conductors. The pixel and common conductors are configured such that, in use, a change in potential difference between the pixel and common conductors in a pixel region induces a change in one or more optical properties of a liquid crystal material in the pixel region.

First claim

What is claimed is:

1. A device, comprising:
a substrate supporting a stack of layers, wherein the stack of layers defines:
source conductors and pixel conductors at a first level;
gate and common conductors at a second level; wherein the first level being between the second level and the substrate;
semiconductor channels between the source conductors and pixel conductors; and
one or more dielectric layers capacitively coupling the semiconductor channels to the gate conductors, wherein the common conductors are located higher in the stack than an uppermost dielectric layer of the one or more dielectric layers; and wherein the pixel conductors and common conductors are configured such that, in use, a change in potential difference between the pixel conductors and common conductors in a pixel region induces a change in one or more optical properties of a liquid crystal material in the pixel region, wherein the device comprises first and second conductor patterns at the first level, and wherein the first conductor pattern defines source conductor lines of the source conductors and the second conductor pattern defines the pixel conductors and extra parts of the source conductors between the source conductor lines and the semiconductor channels, and further wherein the extra parts are parts of the source conductors in closest proximity to the pixel conductors.

2. The device according to claim 1 , comprising third and fourth conductor patterns at the second level, wherein the third and fourth conductor patterns have different designs and exhibit different optical and/or electrical properties.

3. The device according to claim 2 , wherein the third conductor pattern defines the gate conductors; and the fourth conductor pattern defines the common conductors.

4. The device according to claim 3 , wherein the third conductor pattern exhibits a higher electrical conductivity than the fourthsccond conductor pattern, and the fourth conductor pattern exhibits a higher visible light transmittance than the third conductor pattern.

5. The device according to claim 3 , wherein the gate conductors comprise gate conductor lines, and the fourth conductor pattern is over the third conductor pattern in regions of the gate conductor lines.

6. The device according to claim 5 , wherein the pixel conductors comprise pixel conductors for an array of pixels, and wherein the gate conductor lines extend from one edge of the array to an opposite edge of the array.

7. The device according to claim 1 , wherein the first conductor pattern exhibits different optical and/or electrical properties to the second conductor pattern.

8. The device according to claim 7 , wherein the second conductor pattern is formed over the first conductor pattern in regions of the source conductor lines.

9. The device according to claim 8 , wherein the first conductor pattern exhibits a higher electrical conductivity than the second conductor pattern, and the second conductor pattern exhibits a higher visible light transmittance than the first conductor pattern.

10. A display device, comprising a liquid crystal material contained between a device according to claim 1 and a counter component; wherein the pixel and common conductors are configured such that, in use, a change in potential difference between pixel and common conductors in a pixel region induces a change in one or more optical properties of the liquid crystal material in the pixel region.

11. The device according to claim 1 , wherein the common conductors located higher in the stack than the uppermost dielectric layer of the one or more dielectric layers comprise a set of spaced parallel sub-conductors located higher in the stack than the uppermost dielectric layer of the one or more dielectric layers.

12. The device according to claim 11 , wherein the pixel conductor occupies at least all of the area directly beneath the sub-conductors and all of the area directly beneath spaces between the sub-conductors.

13. The device according to claim 1 , wherein the common conductors are formed on the uppermost dielectric layer of the one or more dielectric layers.

14. The device according to claim 1 , comprising a layer of charge-injection organic polymer material on the second conductor pattern.

15. The device according to claim 1 , wherein the pixel conductors comprise pixel conductors for an array of pixels, and wherein the source conductor lines extend from one edge of the array to an opposite edge of the array.

16. The device according to claim 1 , comprising a patterned semiconductor layer defining the semiconductor channels, and a patterned dielectric layer on the semiconductor layer;
wherein the patterned semiconductor layer and the patterned dielectric layer have the same pattern.

17. The device according to claim 1 , wherein the pixel conductors comprise pixel conductors for rows of pixels, and wherein the source conductor lines comprise source conductor lines for respective rows of the rows of pixels.

18. The device according to claim 1 , wherein the pixel conductors and common conductors together provide fringe-field switching electrodes for an array of pixels.

Assignees

• Flexenable Ltd
• Flexenable Tech Limited

Inventors

• Harding James

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/13685

  Top gates · CPC title

• G02F1/13394

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title