Apparatus and method for successive cancellation flip decoding of polar code

Patent metadata

Field	Value
Publication number	US-11764901-B2
Application number	US-202217717766-A
Country	US
Kind code	B2
Filing date	Apr 11, 2022
Priority date	Apr 12, 2021
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Disclosed are an apparatus and method for successive cancellation flip decoding of a polar code. The apparatus for successive cancellation flip decoding of a polar code according to an embodiment includes an iterative unit subtotal matrix generator configured to generate an iterative unit subtotal matrix corresponding to a preset iterative unit size based on a portion of an entire subtotal matrix, a selection logic configured to determine one or more selection bits based on a bit string representing a position of a bit returned when re-decoding and generate an auxiliary matrix for generating the entire subtotal matrix from the one or more selection bits, and an entire subtotal matrix generator configured to generate the entire subtotal matrix by using the iterative unit subtotal matrix and the auxiliary matrix.

First claim

What is claimed is:

1. An apparatus for performing a successive cancellation flip (SCF) decoding of a polar code, the apparatus comprising:
an iterative unit subtotal matrix generator configured to generate an iterative unit subtotal matrix corresponding to a preset iterative unit size based on a fractal structure of an entire subtotal matrix;
a selection logic configured to determine selection bits based on a bit string representing a position of a bit returned when re-decoding a codeword of the polar code after performing a primary decoding of the codeword of the polar code and generate an auxiliary matrix for generating the entire subtotal matrix from the selection bits, the primary decoding including flipping of the bit;
an entire subtotal matrix generator configured to generate the entire subtotal matrix by using the iterative unit subtotal matrix and the auxiliary matrix; and
a memory configured to store the generated iterative unit subtotal matrix,
wherein the selection logic is configured to include a plurality of AND gates and generate the auxiliary matrix through a logic structure of the plurality of AND gates formed by connecting the selection bits with the plurality of AND gates based on a preset operation relation.

2. The apparatus of claim 1 , wherein
the iterative unit subtotal matrix generator is configured to generate the iterative unit subtotal matrix having a size smaller than a size of the entire subtotal matrix.

3. The apparatus of claim 1 , wherein
in the bit string, a position of the bit returned is expressed in a binary system.

4. The apparatus of claim 1 , wherein
the selection logic is configured to determine the selection bits based on bits among remaining bits excluding bits from a least significant bit (LSB) to a bit of a higher digit by a number set based on the preset iterative unit size in a plurality of bits included in the bit string.

5. The apparatus of claim 4 , wherein
the selection logic is configured to determine the selection bits by excluding a most significant bit (MSB) of the bit string from among the remaining bits.

6. The apparatus of claim 1 , wherein
the selection logic is configured to generate selection bit vectors based on the preset operation relation, and generate each column of the auxiliary matrix in ascending order of the columns by substituting the selection bits into the selection bit vectors.

7. A method for performing a successive cancellation flip (SCF) decoding of a polar code by an apparatus for performing the SCF decoding, the apparatus including an iterative unit, a selection logic, an entire subtotal matrix generator and a memory, the method comprising:
generating, by the iterative unit, an iterative unit subtotal matrix corresponding to a preset iterative unit size based on a fractal structure of an entire subtotal matrix;
determining, by the selection logic, selection bits based on a bit string representing a position of a bit returned when re-decoding a codeword of the polar code after performing a primary decoding of the codeword of the polar code, the primary decoding including flipping of the bit;
generating, by the selection logic, an auxiliary matrix for generating the entire subtotal matrix from the selection bits;
storing the generated iterative unit subtotal matrix in the memory; and
generating, by the entire subtotal matrix generator, the entire subtotal matrix by using the iterative unit subtotal matrix and the auxiliary matrix,
wherein the selection logic is configured to include a plurality of AND gates, and
wherein the generating of the auxiliary matrix comprises generating the auxiliary matrix through a logic structure of the plurality of AND gates formed by connecting the selection bits with the plurality of AND gates based on a preset operation relation.

8. The method of claim 7 , wherein
in the generating of the iterative unit subtotal matrix, the iterative unit subtotal matrix having a size smaller than a size of the entire subtotal matrix is generated.

9. The method of claim 7 , wherein
in the bit string, a position of the bit returned is expressed in a binary system.

10. The method of claim 7 , wherein
in the determining of the selection bits,
the selection bits are determined based on bits among remaining bits excluding bits from a least significant bit (LSB) to a bit of a higher digit by a number set based on the preset iterative unit size in a plurality of bits included in the bit string.

11. The method of claim 10 , wherein
in the determining of the selection bits, the selection bits are determined by excluding a most significant bit (MSB) of the bit string from among the remaining bits.

12. The method of claim 7 , wherein
in the generating of the auxiliary matrix, selection bit vectors are generated based on the preset operation relation, and each column of the auxiliary matrix in ascending order of the columns is generated by substituting the selection bits into the selection bit vectors.

Assignees

• Ajou Univ Industry—Academic Cooperation Foundation
• Univ Ajou Ind Academic Coop Found

Inventors

• Sunwoo Myung Hoon
• Roh Jae Hong
• Lee U Seok

Classifications

• H03M13/13 Primary

  Linear codes · CPC title

• H04L1/0057 Primary

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L1/0054

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title