RF front end reduction of receiver de-sensitivity
US-10749565-B1 · Aug 18, 2020 · US
US11764827B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11764827-B2 |
| Application number | US-202117553153-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 16, 2021 |
| Priority date | Sep 6, 2019 |
| Publication date | Sep 19, 2023 |
| Grant date | Sep 19, 2023 |
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A system and method for reducing intermodulation interference between a transmitter circuit and a receiver circuit includes a first hybrid combiner coupled to a transmit port, a second hybrid combiner coupled to an antenna port, a third hybrid combiner coupled to a receive port, a first three port network coupled to the first hybrid combiner, the second hybrid combiner, and the third hybrid combiner, and a second three port network coupled to the first hybrid combiner, the second hybrid combiner, and the third hybrid combiner. Related apparatus, systems, techniques and articles are also described.
Opening claim text (preview).
What is claimed is: 1. A system for reducing intermodulation interference between a transmitter circuit and a receiver circuit, the system comprising: a first hybrid combiner coupled to a transmit port; a second hybrid combiner coupled to an antenna port; a third hybrid combiner coupled to a receive port; a first three port network coupled to the first hybrid combiner, the second hybrid combiner, and the third hybrid combiner; a second three port network coupled to the first hybrid combiner, the second hybrid combiner, and the third hybrid combiner; a first gain block circuit coupled to the first hybrid combiner, the first three port network, and the second three port network; and a second gain block including circuitry, the second gain block coupled to the third hybrid combiner, the first hybrid combiner, and the second hybrid combiner. 2. The system of claim 1 , further comprising control circuitry configured to receive a first receive output signal and a second receive output signal, the control circuitry configured to phase shift and/or attenuate at least one of the first receive output signal and/or the second receive output signal. 3. The system of claim 2 , wherein the control circuitry includes at least one phase shifter and at least one attenuator. 4. The system of claim 2 , further comprising control logic configured to: receive a first signal characterizing a transmit signal level at the transmit port; receive a second signal characterizing a receive signal level at the receive port; and control the control circuitry to reduce a level of transmit signal at the receive port. 5. The system of claim 2 , further comprising control logic configured to: receive a first signal characterizing a receive signal level at the receive port; determine intermodulation signal components of the first signal; and control the control circuitry to reduce a level of intermodulation signal component at the receive port. 6. The system of claim 2 , further comprising control logic configured to: receive a first signal characterizing a transmit signal level at the transmit port; receive a second signal characterizing a receive signal level at the receive port; determine intermodulation signal components of the second signal; and control the control circuitry to reduce a level of transmit signal at the receive port and to reduce a level of intermodulation signal component at the receive port. 7. The system of claim 2 , wherein the control circuitry is formed as one or more application specific integrated circuits (ASICs).
with means for reducing leakage of transmitter signal into the receiver · CPC title
the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder · CPC title
Suppression or limitation of noise or interference (by means associated with receiver H04B1/10) · CPC title
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