Radio transceiver control interface

Patent metadata

Field	Value
Publication number	US-11764822-B2
Application number	US-202117305999-A
Country	US
Kind code	B2
Filing date	Jul 19, 2021
Priority date	Aug 6, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.

First claim

What is claimed is:

1. A transceiver integrated circuit (IC) comprising:
a plurality of transmitters;
a plurality of receivers;
a plurality of common pins configured to receive an input data vector for controlling channel settings of the plurality of transmitters and the plurality of receivers, the input data vector received in parallel on the plurality of common pins, wherein a total number of the plurality of common pins is smaller than a total number of the plurality of transmitters and the plurality of receivers; and
a control circuit configured to convert the input data vector to digitized values of signals and to map the digitized values of signals to a first plurality of channel settings of the plurality of transmitters and to a second plurality of channel settings of the plurality of receivers.

2. The transceiver IC of claim 1 , wherein the first plurality of channel settings include a plurality of transmitter enable settings for individually enabling each of the plurality of transmitters, and the second plurality of channel settings include a plurality of receiver enable settings for individually enabling each of the plurality of receivers.

3. The transceiver IC of claim 1 , wherein the first plurality of channel settings include a plurality of frequency conversion settings for each of the plurality of transmitters.

4. The transceiver IC of claim 3 , wherein the plurality of frequency conversion settings include at least one numerically controlled oscillator (NCO) setting.

5. The transceiver IC of claim 1 , wherein the second plurality of channel settings include a plurality of frequency conversion settings for each of the plurality of receivers.

6. The transceiver IC of claim 1 , wherein the first plurality of channel settings include a plurality of gain settings of the plurality of transmitters, and the second plurality of channel settings include a plurality of gain settings of the plurality of receivers.

7. The transceiver IC of claim 1 , further comprising at least one observation receiver having a third plurality of channel settings, the control circuit further configured to map the digitized values of signals to the third plurality of channel settings.

8. The transceiver IC of claim 1 , further comprising a plurality of registers storing the first plurality of channel settings and the second plurality of channel settings, wherein the control circuit comprises a register mapping circuit.

9. The transceiver IC of claim 8 , wherein the register mapping circuit comprises a register mapping table storing data mapping the digitized values of signals to data stored in the plurality of registers.

10. The transceiver IC of claim 1 , wherein the control circuit comprises a plurality of analog-to-digital converters configured to convert the input data vector to the digitized values of signals.

11. A radio frequency (RF) communication system comprising:
a front-end system configured to receive a plurality of RF transmit signals, and to provide a plurality of RF receive signals; and
a transceiver comprising:
a plurality of transmitters configured to generate the plurality of RF transmit signals for the front-end system;
a plurality of receivers configured to receive the plurality of RF receive signals from the front-end system;
a plurality of common pins configured to receive an input data vector for controlling channel settings of the plurality of transmitters and the plurality of receivers, the input data vector received in parallel on the plurality of common pins, wherein a total number of the plurality of common pins is smaller than a total number of the plurality of transmitters and the plurality of receivers; and
a control circuit configured to convert the input data vector to digitized values of signals and to map the digitized values of signals to a first plurality of channel settings of the plurality of transmitters and to a second plurality of channel settings of the plurality of receivers.

12. The RF communication system of claim 11 , wherein the RF communication system further comprises a baseband processor configured to provide in-phase (I) transmit data and quadrature-phase (Q) transmit data to the plurality of transmitters, and to receive I receive data and Q receive data from the plurality of receivers.

13. The RF communication system of claim 11 , wherein the first plurality of channel settings include a plurality of transmitter enable settings for individually enabling each of the plurality of transmitters, and the second plurality of channel settings include a plurality of receiver enable settings for individually enabling each of the plurality of receivers.

14. A method of transceiver configuration, the method comprising:
receiving an input data vector for controlling channel settings of a plurality of transmitters and a plurality of receivers on a plurality of common pins of a transceiver IC, the input data vector received in parallel on the plurality of common pins, wherein a total number of the plurality of common pins is smaller than a total number of the plurality of transmitters and the plurality of receivers;
converting the input data vector to digitized values of signals using a control circuit of the transceiver IC; and
mapping the digitized values of signals to a first plurality of channel settings of the plurality of transmitters and to a second plurality of channel settings of the plurality of receivers using the control circuit of the transceiver IC.

15. The method of claim 14 , wherein the first plurality of channel settings include a plurality of transmitter enable settings for individually enabling each of the plurality of transmitters, and the second plurality of channel settings include a plurality of receiver enable settings for individually enabling each of the plurality of receivers.

16. The method of claim 14 , wherein the first plurality of channel settings include a plurality of frequency conversion settings for each of the plurality of transmitters, and the second plurality of channel settings include a plurality of frequency conversion settings for each of the plurality of receivers.

17. The method of claim 14 , wherein the first plurality of channel settings include a plurality of gain settings of the plurality of transmitters, and the second plurality of channel settings include a plurality of gain settings of the plurality of receivers.

18. The method of claim 14 , further comprising mapping the digitized values of signals to a third plurality of channel settings of at least one observation receiver using the control circuit of the transceiver IC.

19. The method of claim 14 , further comprising storing the first plurality of channel settings and the second plurality of channel settings in a plurality of registers of the transceiver IC.

20. The method of claim 19 , further comprising mapping the digitized values of signals to data stored in the registers using a mapping table.

Assignees

• Analog Devices Inc

Inventors

• Mayer Christopher
• Manglani Manish J

Classifications

• H04B1/40 Primary

  Circuits · CPC title