Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer
US-9455737-B1 · Sep 27, 2016 · US
US11764803B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11764803-B2 |
| Application number | US-202217706012-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 28, 2022 |
| Priority date | Jan 16, 2017 |
| Publication date | Sep 19, 2023 |
| Grant date | Sep 19, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.
Opening claim text (preview).
The invention claimed is: 1. A digital-to-analog conversion device comprising: circuitry including: an integrator that is configured to perform integration processing for integrating a difference between an input signal and a first return signal and a second return signal generated based on the input signal, to thereby generate an integration result; a first quantizer that is configured to perform first quantization processing for quantizing the integration result generated by the integrator, to thereby generate a first quantization signal; and an output section that is configured to perform output processing for outputting output signals including a Pulse Width Modulation (PWM) signal whose pulse width is asymmetrical to a center of a processing period, based on the first quantization signal generated by the quantization of the first quantization processing, wherein the first return signal delays the first quantization signal, wherein the second return signal delays a correction value signal outputted based on the integration result generated by the integrator, and wherein the correction value signal includes a signal indicating a correction value for correcting a difference between (i) a center of the pulse width asymmetrical to the center of the processing period and (ii) the center of the processing period. 2. A digital-to-analog conversion method for a digital-to-analog conversion device comprising circuitry including an integrator, a first quantizer, and an output section, the method comprising: performing, by the integrator, integration processing for integrating a difference between an input signal and a first return signal and a second return signal generated based on the input signal, to thereby generate an integration result; performing, by the first quantizer, first quantization processing for quantizing the integration result generated by the integrator, to thereby generate a first quantization signal; and performing, by the output section, output processing for outputting output signals including a Pulse Width Modulation (PWM) signal whose pulse width is asymmetrical to a center of a processing period, based on a first quantization signal generated by the quantization of the first quantization processing, wherein the first return signal delays the first quantization signal, wherein the second return signal delays a correction value signal outputted based on the integration result generated by the integrator, and wherein the correction value signal includes a signal indicating a correction value for correcting a difference between (i) a center of the pulse width asymmetrical to the center of the processing period and (ii) the center of the processing period. 3. The digital-to-analog conversion device according to claim 1 , wherein the pulse width includes a first period that comes before a timing at the center of the processing period and a second period that comes after the timing at the center of the processing period, and wherein the first period and the second period have different time lengths. 4. An electronic musical instrument comprising: the digital-to-analog conversion device according to claim 1 ; a keyboard; and a sound emission section which emits a musical sound subjected to digital-to-analog conversion based on an output from the digital-to-analog conversion device. 5. An information processing apparatus comprising: the digital-to-analog conversion device according to claim 1 ; and a sound emission section which emits a musical sound subjected to digital-to-analog conversion based on an output from the digital-to-analog conversion device. 6. The digital-to-analog conversion device according to claim 1 , the circuitry further including: a first subtractor that is configured to perform first subtraction processing for obtaining the difference between the input signal and the first return signal, to thereby generate a first subtraction processing result. 7. The digital-to-analog conversion device according to claim 6 , the circuitry further including: a second subtractor that is configured to perform second subtraction processing for obtaining a difference between the first subtraction processing result and the second return signal, to thereby generate a second subtraction processing result. 8. The digital-to-analog conversion device according to claim 7 , the circuitry further including: a first delay section that is configured to perform first delay processing for generating a correction value delay signal by delaying the correction value signal, and outputting the correction value delay signal; and a second delay section that is configured to perform second delay processing for generating the first return signal by delaying the first quantization signal, and outputting the first return signal to the first subtractor. 9. The digital-to-analog conversion device according to claim 8 , the circuitry further including: a third delay section that is configured to perform third delay processing for generating the second return signal by delaying the correction value delay signal output by the first delay section.
the final digital/analogue converter being constituted by a pulse width modulator · CPC title
Input signal integrated with linear return to datum · CPC title
Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} · CPC title
Structural association with individual keys (electrically operated wind-actuated organs G10B3/22) · CPC title
by calculating functions or polynomial approximations to evaluate amplitudes at successive sample points of a tone waveform · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.