Distributed circuit

Patent metadata

Field	Value
Publication number	US-11764744-B2
Application number	US-202017598379-A
Country	US
Kind code	B2
Filing date	Mar 13, 2020
Priority date	Mar 29, 2019
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.

First claim

The invention claimed is:

1. A distributed circuit comprising:
a first transmission line configured to receive an input signal at an input end;
a second transmission line configured to output an output signal from an output end;
a termination resistor connected to a line end of the first transmission line;
a plurality of unit cells arranged along the first and second transmission lines, the unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, wherein each of the unit cells comprises:
an input transistor having a base terminal connected to the first transmission line; and
an emitter resistor connected to an emitter terminal of the input transistor; and

a bias tee connected to the input end of the first transmission line, the bias tee configured to supply a bias voltage to the input transistor of each of the unit cells, wherein the emitter resistor of each of the unit cells is set to a different resistance value from each other, the different resistance value being set based on a distance between the respective unit cell and the bias tee, so that a collector current flowing through the input transistor of each of the unit cells has a uniform value.

2. The distributed circuit according to claim 1 , wherein when a current flows from the bias tee toward the termination resistor through the first transmission line, the emitter resistor of each of the unit cells is set to a larger resistance value as the corresponding unit cell is closer to the bias tee and to a smaller resistance value as the corresponding unit cell is closer to the termination resistor.

3. The distributed circuit according to claim 1 , wherein when a current flows from the termination resistor toward the bias tee through the first transmission line, the emitter resistor of each of the unit cells is set to a smaller resistance value as the corresponding unit cell is closer to the bias tee and to a larger resistance value as the corresponding unit cell is closer to the termination resistor.

4. The distributed circuit according to claim 1 , wherein each of the unit cells further comprises:
the emitter resistor having a first end connected to the emitter terminal of the input transistor and a second end connected to a first voltage; and
an output transistor having a base terminal connected to a second voltage, a collector terminal connected to the second transmission line, and an emitter terminal connected to the collector terminal of the input transistor; and
wherein the distributed circuit is configured to operate as a distributed amplifier.

5. The distributed circuit according to claim 1 , wherein the input signal is an intermediate frequency (IF) signal and the output signal is a radio frequency (RF) signal, and the distributed circuit further comprises a third transmission line configured to receive a local oscillator (LO) signal at an input end.

6. The distributed circuit according to claim 5 , wherein each of the unit cells further comprises:
an output transistor having a base terminal connected to the third transmission line, a collector terminal connected to the second transmission line, and an emitter terminal connected to the collector terminal of the input transistor; and
the emitter resistor having a first end connected to the emitter terminal of the input transistor and a second end connected to a first voltage; and
wherein the distributed circuit is configured to operate as a distributed mixer.

7. The distributed circuit according to claim 1 , wherein the bias tee comprises:
a capacitor having a first end configured to receive the input signal and a second end connected to the input end of the first transmission line; and
an inductor having a first end connected to the input end of the first transmission line and a second end connected to a third voltage.

8. A distributed circuit comprising:
a first transmission line configured to receive an input signal at an input end;
a second transmission line configured to output an output signal from an output end;
a termination resistor connected to a line end of the first transmission line;
a plurality of unit cells arranged along the first and second transmission lines, the unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, wherein each of the unit cells comprises:
an input transistor having a gate terminal connected to the first transmission line; and
a source resistor connected to a source terminal of the input transistor; and

a bias tee connected to the input end of the first transmission line, the bias tee configured to supply a bias voltage to the input transistor of each of the unit cells, wherein the source resistor of each of the unit cells is set to a different resistance value from each other, the different resistance value being set based on a distance between the respective unit cell and the bias tee, so that a drain current flowing through the input transistor of each of the unit cells has a uniform value.

9. The distributed circuit according to claim 8 , wherein when a current flows from the bias tee toward the termination resistor through the first transmission line, the source resistor of each of the unit cells is set to a larger resistance value as the corresponding unit cell is closer to the bias tee and to a smaller resistance value as the corresponding unit cell is closer to the termination resistor.

10. The distributed circuit according to claim 8 , wherein when a current flows from the termination resistor toward the bias tee through the first transmission line, the source resistor of each of the unit cells is set to a smaller resistance value as the corresponding unit cell is closer to the bias tee and to a larger resistance value as the corresponding unit cell is closer to the termination resistor.

11. The distributed circuit according to claim 8 , wherein each of the unit cells further comprises:
the source resistor having a first end connected to the source terminal of the input transistor and a second end connected to a first voltage; and
an output transistor having a gate terminal connected to a second voltage, a drain terminal connected to the second transmission line, and a source terminal connected to the drain terminal of the input transistor; and
wherein the distributed circuit is configured to operate as a distributed amplifier.

12. The distributed circuit according to claim 8 , wherein the input signal is an intermediate frequency (IF) signal and the output signal is a radio frequency (RF) signal, and the distributed circuit further comprises a third transmission line configured to receive a local oscillator (LO) signal at an input end.

13. The distributed circuit according to claim 12 , wherein each of the unit cells further comprises:
an output transistor having a gate terminal connected to the third transmission line, a drain terminal connected to the second transmission line, and a source terminal connected to the drain terminal of the input transistor; and
the source resistor having a first end connected to the source terminal of the input transistor and a second end connected to a first voltage; and
wherein the distributed circuit is configured to operate as a distributed mixer.

14. The distributed circuit according to claim 8 , wherein the bias tee comprises:
a capacitor having a first end configured to receive the input signal and a second end connected to the input end of the first transmission line; and
an inductor having a first end connected to the input end of the firs

Assignees

• Nippon Telegraph & Telephone

Inventors

• Jo Teruo
• Nagatani Munehiko
• Nosaka Hideyuki

Classifications

• H03F3/605 Primary

  Distributed amplifiers · CPC title

• H03F1/22

  by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively · CPC title

• H03F1/18

  by use of distributed coupling {, i.e. distributed amplifiers (distributed amplifiers using coupling networks with distributed constants H03F3/605)} · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03D7/1433

  using bipolar transistors (H03D7/145 takes precedence) · CPC title