Signal combiner having a tuned termination circuit on an isolation port for a Doherty power amplifier

Patent metadata

Field	Value
Publication number	US-11764734-B2
Application number	US-202117411034-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Aug 13, 2014
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

The disclosure relates to a signal combiner for a Doherty power amplifier architecture, the signal combiner including a termination circuit on an isolation port, the termination circuit being tuned to improve performance of the Doherty power amplifier. The architecture includes a carrier amplifier and a peaking amplifier. The peaking amplifier modulates the load seen by the carrier amplifier, allowing the carrier amplifier to remain in high-efficiency, saturated operation even at back-off. This load modulation can be achieved using impedance matching networks having an impedance matched to a specific frequency. The architectures include tuned or tailored signal combiners with termination circuits on isolation ports. The termination circuits are tuned or tailored for particular operating frequencies to enhance operation.

First claim

What is claimed is:

1. An amplifier architecture comprising:
a signal input port configured to receive an input signal to be amplified, the input signal having an operating frequency;
a splitter configured to split the input signal into a first signal and a second signal, to direct the first signal along a carrier amplifier path, and to direct the second signal along a peaking amplifier path;
a carrier amplifier coupled to the splitter and disposed along the carrier amplifier path, the carrier amplifier configured to amplify the first signal;
a peaking amplifier coupled to the splitter and disposed along the peaking amplifier path, the peaking amplifier configured to amplify the second signal; and
a signal combiner including a first port configured to receive the amplified first signal, a second port coupled to a signal output port to output an amplified output signal that is a combination of the first amplified signal and the second amplified signal, a third port coupled to ground through a termination circuit with a termination capacitor having a fixed capacitance that is approximately equal to a multiplicative inverse of 2 times pi times an operating frequency of the amplifier architecture times a characteristic impedance of a load coupled to the amplifier architecture, and a fourth port configured to receive the amplified second signal.

2. The amplifier architecture of claim 1 wherein the signal combiner further includes a first capacitor between the first port and the third port and a second capacitor between the second port and the fourth port.

3. The amplifier architecture of claim 2 wherein the termination capacitor has a capacitance that is twice the capacitance of the first capacitor or the second capacitor.

4. The amplifier architecture of claim 2 wherein a capacitance of the first capacitor is equal to a capacitance of the second capacitor.

5. The amplifier architecture of claim 1 wherein the signal combiner further includes a transformer having a first coil between the first port and the second port and a second coil between the third port and the fourth port.

6. The amplifier architecture of claim 5 wherein the transformer comprises a balun transformer.

7. The amplifier architecture of claim 1 wherein the termination circuit further includes a harmonic rejection circuit configured to reduce a strength of one or more harmonics at the second port.

8. The amplifier architecture of claim 7 wherein the harmonic rejection circuit includes a plurality of resonant elements connected in series.

9. An amplifier architecture comprising:
a signal input port configured to receive an input signal to be amplified, the input signal having an operating frequency;
a splitter configured to split the input signal into a first signal and a second signal, to direct the first signal along a carrier amplifier path, and to direct the second signal along a peaking amplifier path;
a carrier amplifier coupled to the splitter and disposed along the carrier amplifier path, the carrier amplifier configured to amplify the first signal;
a peaking amplifier coupled to the splitter and disposed along the peaking amplifier path, the peaking amplifier configured to amplify the second signal; and
a signal combiner including a first port configured to receive the amplified first signal, a second port coupled to a signal output port to output an amplified output signal that is a combination of the first amplified signal and the second amplified signal, a third port coupled to ground through a termination circuit with a capacitance whose reactance is equal in magnitude to a characteristic impedance of the amplifier architecture, and a fourth port configured to receive the amplified second signal.

10. The amplifier architecture of claim 9 wherein the signal combiner further includes a first capacitor between the first port and the third port and a second capacitor between the second port and the fourth port.

11. The amplifier architecture of claim 10 wherein the termination circuit includes a termination capacitor that has a capacitance that is twice the capacitance of the first capacitor or the second capacitor.

12. The amplifier architecture of claim 10 wherein a capacitance of the first capacitor is equal to a capacitance of the second capacitor.

13. The amplifier architecture of claim 9 wherein the signal combiner further includes a transformer having a first coil between the first port and the second port and a second coil between the third port and the fourth port.

14. The amplifier architecture of claim 9 wherein the termination circuit further includes a harmonic rejection circuit configured to reduce a strength of one or more harmonics at the second port.

15. The amplifier architecture of claim 14 wherein the harmonic rejection circuit includes a plurality of resonant elements connected in series.

16. An amplifier architecture comprising:
a signal input port configured to receive an input signal to be amplified, the input signal having an operating frequency;
a splitter configured to split the input signal into a first signal and a second signal, to direct the first signal along a peaking amplifier path, and to direct the second signal along a carrier amplifier path;
a peaking amplifier coupled to the splitter and disposed along the peaking amplifier path, the peaking amplifier configured to amplify the first signal;
a carrier amplifier coupled to the splitter and disposed along the carrier amplifier path, the carrier amplifier configured to amplify the second signal; and
a signal combiner including a first port configured to receive the amplified first signal, a second port coupled to a signal output port to output an amplified output signal that is a combination of the first amplified signal and the second amplified signal, a third port coupled to ground through a termination circuit with a termination inductor having a fixed inductance that is approximately equal to a characteristic impedance of a load coupled to the amplifier architecture divided by 2 times pi times an operating frequency of the amplifier architecture, and a fourth port configured to receive the amplified second signal.

17. The amplifier architecture of claim 16 wherein the signal combiner further includes a first capacitor between the first port and the third port and a second capacitor between the second port and the fourth port.

18. The amplifier architecture of claim 17 wherein a capacitance of the first capacitor is equal to a capacitance of the second capacitor.

19. The amplifier architecture of claim 16 wherein the signal combiner further includes a transformer having a first coil between the first port and the second port and a second coil between the third port and the fourth port.

20. The amplifier architecture of claim 19 wherein the transformer comprises a balun transformer.

Assignees

• Skyworks Solutions Inc

Inventors

• Datta Kunal
• Kasnavi Reza
• Lyalin Aleksey A

Classifications

• H03F1/0288 Primary

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F2200/111

  the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not · CPC title

• H03F2203/7209

  the gated amplifier being switched from a first band to a second band · CPC title