Semiconductor packages including at least one die position checker

Patent metadata

Field	Value
Publication number	US-11764160-B2
Application number	US-202117148436-A
Country	US
Kind code	B2
Filing date	Jan 13, 2021
Priority date	Jul 29, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first die disposed on a package substrate;
a second die stacked on the first die; and
first and second position checkers disposed on the package substrate to be spaced apart from the first and second dies,
wherein the first position checker indicates a first position allowable range in which a first side of the first die can be located, and
wherein the second position checker indicates a second position allowable range in which a second side of the second die can be located.

2. The semiconductor package of claim 1 , wherein the first position checker comprises:
a first reference pattern indicating a first reference position where the first side of the first die is to be located; and
a first limit pattern spaced apart from the first reference pattern by the first position allowable range.

3. The semiconductor package of claim 2 , wherein the second position checker comprises:
a second reference pattern indicating a second reference position where the second side of the second die is to be located; and
a second limit pattern spaced apart from the second reference pattern by the second position allowable range.

4. The semiconductor package of claim 3 , wherein the first limit pattern and the second limit pattern are disposed to face each other between the first reference pattern and the second reference pattern.

5. The semiconductor package of claim 3 , wherein the first limit pattern and the second limit pattern have line shapes extending substantially in parallel.

6. The semiconductor package of claim 5 , wherein the first reference pattern and the second reference pattern have substantially the same shape, and the first limit pattern and the second limit pattern have substantially the same shape.

7. The semiconductor package of claim 3 , wherein the first reference pattern has a line shape, and the first limit pattern has a dotted shape substantially parallel to the line shape.

8. The semiconductor package of claim 1 , further comprising a first fiducial mark and a second fiducial mark disposed on the package substrate.

9. The semiconductor package of claim 1 , wherein the second die is offset stacked from the first die such that a portion of the first die, adjacent to the first side of the first die is exposed outside the second side.

10. The semiconductor package of claim 9 , wherein the first die further comprises bonding pads disposed in the portion, and
wherein the package substrate further comprises bonding fingers connected to the bonding pads by bonding wires.

11. The semiconductor package of claim 1 , further comprising third and fourth position checkers disposed on the package substrate,
wherein the third position checker indicates a third position allowable range in which a third side crossing the first side of the first die can be located, and
wherein the fourth position checker indicates a fourth position allowable range in which a fourth side crossing the second side of the second die can be located.

12. The semiconductor package of claim 1 , further comprising fifth and sixth position checkers disposed at positions opposite to the positions where the first and second position checkers are located, with the first and second dies therebetween.

13. A semiconductor package comprising:
a first die disposed on a package substrate;
a second die stacked on the first die to be offset in a Y-axis direction; and
first and second position checkers disposed on the package substrate,
wherein the first and second position checkers are disposed to be spaced apart from the first and second dies in an X-axis direction, and
wherein the second position checker is disposed to be spaced apart from the first position checker in the Y-axis direction.

14. The semiconductor package of claim 13 , wherein the first position checker indicates a first position allowable range in which a first side of the first die can be located, and
wherein the second position checker indicates a second position allowable range in which a second side of the second die can be located.

15. The semiconductor package of claim 13 , wherein the first position checker comprises:
a first reference pattern indicating a first reference position where the first side of the first die is to be located; and
a first limit pattern spaced apart from the first reference pattern by the first position allowable range in the Y-axis direction.

16. The semiconductor package of claim 15 , wherein the first reference pattern and the first limit pattern are patterns extending substantially in parallel in the X-axis direction.

17. A semiconductor package comprising;
a first die disposed on a package substrate;
a second die stacked on the first die and offset stacked by a distance from the first die; and
a first position checker disposed on the package substrate to be and spaced apart from the first and second dies,
wherein the first position checker indicates a first position allowable range in which a first side of the first die can be located to have a normal separation distance from a second side of the second die.

Assignees

• Sk Hynix Inc

Inventors

• Min Bok Gyu
• Lee Suk Won

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title