Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11764126-B2
Application number	US-201817280756-A
Country	US
Kind code	B2
Filing date	Nov 12, 2018
Priority date	Nov 12, 2018
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first semiconductor package; and
a second semiconductor package, wherein
the first semiconductor package includes:
a first exposed surface on which a surface of a first metal block stacked on a first semiconductor chip is exposed;
a second exposed surface on which a surface of a second metal block not stacked on the first semiconductor chip is exposed from a same side as the first exposed surface; and
a first heat dissipation surface located on an opposite side to the first exposed surface and the second exposed surface, the first heat dissipation surface being insulated from an internal structure including the first semiconductor chip, the first metal block, and the second metal block,

the second semiconductor package includes:
a third exposed surface on which a surface of a third metal block stacked on a second semiconductor chip is exposed;
a fourth exposed surface on which a surface of a fourth metal block not stacked on the second semiconductor chip is exposed from a same side as the third exposed surface; and
a second heat dissipation surface located on an opposite side to the third exposed surface and the fourth exposed surface, the second heat dissipation surface being insulated from an internal structure including the second semiconductor chip, the third metal block, and the fourth metal block, and

the second semiconductor package is joined on the first semiconductor package in such a manner that the first exposed surface of the first semiconductor package and the fourth exposed surface of the second semiconductor package are connected so as to face each other, and the second exposed surface of the first semiconductor package and the third exposed surface of the second semiconductor package are connected so as to face each other.

2. The semiconductor device according to claim 1 , wherein
the first semiconductor package includes:
a first heat spreader having a surface on which the first semiconductor chip and the first metal block are sequentially stacked;
a first insulating film having a surface provided with the first heat spreader and the second metal block adjacent to the first heat spreader; and
a first resin part enclosing the first insulating film, the first heat spreader, the first semiconductor chip, the first metal block, and the second metal block, and having a surface from which the first exposed surface of the first metal block and the second exposed surface of the second metal block are exposed, and

the second semiconductor package includes:
a second heat spreader having a surface on which the second semiconductor chip and the third metal block are sequentially stacked;
a second insulating film having a surface provided with the second heat spreader and the fourth metal block adjacent to the second heat spreader; and
a second resin part enclosing the second insulating film, the second heat spreader, the second semiconductor chip, the third metal block, and the fourth metal block, and having a surface from which the third exposed surface of the third metal block and the fourth exposed surface of the fourth metal block are exposed.

3. The semiconductor device according to claim 2 , wherein
the first heat spreader and the second metal block of the first semiconductor package are integrated with each other, and
the second exposed surface of the second metal block is the surface of the first heat spreader.

4. The semiconductor device according to claim 1 , wherein the first semiconductor package and the second semiconductor package joined on the first semiconductor package constitute a structure having two-fold symmetry in a sectional view.

5. The semiconductor device according to claim 1 , further comprising a joining layer containing gold (Au), the joining layer joining the first exposed surface of the first semiconductor package and the fourth exposed surface of the second semiconductor package together and joining the second exposed surface of the first semiconductor package and the third exposed surface of the second semiconductor package together.

6. The semiconductor device according to claim 1 , further comprising a low melting point solder that joins the first exposed surface of the first semiconductor package and the fourth exposed surface of the second semiconductor package together and joins the second exposed surface of the first semiconductor package and the third exposed surface of the second semiconductor package together, wherein
the low melting point solder has a melting point that is lower than a melting point of a solder that fixes the first semiconductor chip inside the first semiconductor package or of a solder that fixes the second semiconductor chip inside the second semiconductor package.

7. The semiconductor device according to claim 1 , further comprising conductive grease that joins the first exposed surface of the first semiconductor package and the fourth exposed surface of the second semiconductor package together and joins the second exposed surface of the first semiconductor package and the third exposed surface of the second semiconductor package together.

8. The semiconductor device according to claim 1 , further comprising a silver paste that joins the first exposed surface of the first semiconductor package and the fourth exposed surface of the second semiconductor package together and joins the second exposed surface of the first semiconductor package and the third exposed surface of the second semiconductor package together.

9. The semiconductor device according to claim 1 , wherein
the first exposed surface and the second exposed surface of the first semiconductor package are located in a same plane, and
the third exposed surface and the fourth exposed surface of the second semiconductor package are located in a same plane.

10. The semiconductor device according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip include silicon carbide (SiC).

11. The semiconductor device according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip include a reverse conducting insulated gate bipolar transistor (RC-IGBT).

12. The semiconductor device according to claim 1 , further comprising:
a first cooler joined to the first heat dissipation surface of the first semiconductor package through grease; and
a second cooler joined to the second heat dissipation surface of the second semiconductor package through grease and connected to the first cooler by screws, wherein,
by fastening the screws, the first cooler and the first semiconductor package are in contact with each other while applying pressure, and the second cooler and the second semiconductor package are in contact with each other while applying pressure.

13. The semiconductor device according to claim 12 , wherein the first semiconductor package and the second semiconductor package include through holes through which the screws penetrate respectively.

14. The semiconductor device according to claim 1 , further comprising:
a first cooler joined to the first heat dissipation surface of the first semiconductor package through a solder or a brazing material; and
a second cooler joined to the second heat dissipation surface of the second semiconductor package through a solder or a brazing material.

15. A method of manufacturing a semiconductor device comprising the steps:
preparing a first semiconductor package including a first exposed surface on which a surface of a first metal block stacked on a first semiconductor chip is exposed, a second exposed surfac

Assignees

• Mitsubishi Electric Corp

Inventors

• KOMO Hideo
• Omaru Takeshi
• TSURU Takuya

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07331

  Connecting techniques · CPC title