Method of forming a through-substrate via and a semiconductor device comprising a through-substrate via

Patent metadata

Field	Value
Publication number	US-11764109-B2
Application number	US-201916980197-A
Country	US
Kind code	B2
Filing date	Apr 3, 2019
Priority date	Apr 4, 2018
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.

First claim

The invention claimed is:

1. A method of forming a through-substrate via, comprising:
providing a substrate with a dielectric arranged on the substrate, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer, the metallic layer being disposed between the substrate and the metal layer,
forming a via hole penetrating the substrate above the metal layer;
removing the dielectric from above the metallic layer so that the via hole reaches the metallic layer;
applying an insulation layer in the via hole and on the metallic layer after removing the dielectric;
removing the insulation layer from above a contact area of the metal layer such that a portion of the metallic layer is left between the metal layer and the insulation layer; and
applying a metallization in the via hole, the metallization contacting the metal layer in the contact area and being insulated from the substrate by the insulation layer, wherein
the metallic layer is completely removed from the contact area before the metallization is applied.

2. The method of claim 1 , wherein
the metal layer comprises a material that is different from the material of the metallic layer.

3. The method of claim 1 , wherein
the metallic layer comprises titanium or aluminum.

4. The method of claim 1 , wherein
the metallic layer comprises a nitride.

5. The method of claim 1 , wherein
the dielectric is removed from above the metal layer by etching and by using a recipe that is non-selective with respect to the metallic layer.

6. The method of claim 1 , wherein
the metal layer is aluminum.

7. The method of claim 1 , wherein
the dielectric and the insulation layer are removed from above the metal layer by etching, and in each of these etching steps the same etching recipe is used.

8. The method of claim 1 , further comprising:
before forming the via hole, applying a mask with an opening;
etching the via hole through the opening; and
removing the mask before the insulation layer is applied.

9. A semiconductor device, comprising:
a substrate with a through-substrate via;
a via hole of the through-substrate via;
an insulation layer in the via hole;
a metallization of the through-substrate via, the insulation layer insulating the metallization from the substrate;
a metal layer above the substrate, the metallization contacting the metal layer; and
a metallic layer on the metal layer, the metallic layer being arranged between the substrate and the metal layer, the metallic layer comprising a material that is different from the material of the metal layer, wherein
a portion of the metallic layer is arranged between the metal layer and the insulation layer and is in physical contact with the insulation layer, and
the metallization is in physical contact with a contact area of the metal layer.

10. The semiconductor device according to claim 9 , wherein the metallic layer comprises titanium or aluminum.

11. The semiconductor device according to claim 9 , wherein the metallic layer comprises a nitride.

Assignees

• Ams Ag

Inventors

• Kraft Jochen
• Parteder Georg
• Jessenig Stefan
• Schrank Franz
• Siegert Jörg

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title