Multilayer capacitor and board having the same mounted thereon

Patent metadata

Field	Value
Publication number	US-11763987-B2
Application number	US-202117356110-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Dec 30, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with each of the plurality of dielectric layers interposed therebetween, and an external electrode disposed on the capacitor body to be connected to the internal electrode. At least one intermetallic compound layer is disposed in a region in which the plurality of internal electrodes and the external electrode are connected, and a total number of the at least one intermetallic compound layer is more than or equal to 55% and less than 100% of a total number of the plurality of internal electrodes.

First claim

What is claimed is:

1. A multilayer capacitor comprising:
a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with each of the plurality of dielectric layers interposed therebetween; and
an external electrode disposed on the capacitor body to be connected to the plurality of internal electrodes,
wherein at least one intermetallic compound layer is disposed in a region in which the plurality of internal electrodes and the external electrode are connected,
a total number of the at least one intermetallic compound layer is more than or equal to 55% and less than 100% of a total number of the plurality of internal electrodes, and
a ratio of an average thickness of the at least one intermetallic compound layer to an average thickness of an internal electrode is 50% or more and less than 90%.

2. The multilayer capacitor of claim 1 , wherein the total number of the at least one intermetallic compound layer is 55% to 99% of the total number of the plurality of internal electrodes.

3. The multilayer capacitor of claim 1 , wherein the capacitor body comprises first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, perpendicular to the first direction, and fifth and sixth surfaces opposing each other in a third direction, perpendicular to the first and second directions,
wherein in the third and fourth surfaces of capacitor body, a plurality of grooves are disposed between the dielectric layers disposed in the first direction, and
the at least one intermetallic compound layer is disposed in the grooves.

4. The multilayer capacitor of claim 3 , wherein an average depth of the plurality of grooves is 30 μm or more.

5. The multilayer capacitor of claim 1 , wherein an average depth of portions of the external electrode that diffuse to the plurality of internal electrodes, on connection portions between the plurality of internal electrodes and the external electrode, is 30 μm or more.

6. The multilayer capacitor of claim 1 , wherein the external electrode comprises:
an electrode layer disposed on the capacitor body and in contact with the at least one intermetallic compound layer; and
a conductive resin layer disposed on the electrode layer and including a plurality of metal particles, a conductive connection portion surrounding each of the plurality of metal particles and contacting the electrode layer, and a base resin.

7. The multilayer capacitor of claim 6 , wherein the plurality of metal particles of the conductive resin layer include at least one of copper, nickel, silver, silver-coated copper, or tin-coated copper.

8. The multilayer capacitor of claim 6 , wherein the plurality of metal particles of the conductive resin layer have one of a spherical shape, a flake shape, or a mixture of the spherical shape and the flake shape.

9. The multilayer capacitor of claim 6 , wherein the external electrode further comprises a plating layer disposed on the conductive resin layer.

10. The multilayer capacitor of claim 9 , wherein the plating layer comprises a nickel plating layer and a tin plating layer, sequentially stacked on the conductive resin layer.

11. The multilayer capacitor of claim 1 , wherein each of the plurality of internal electrodes includes nickel, and the at least one intermetallic compound layer includes nickel-copper (Ni—Cu).

12. A board having a multilayer capacitor mounted thereon, the board comprising:
a substrate having a plurality of electrode pads on one surface of the substrate; and
the multilayer capacitor of claim 1 , mounted on the substrate, wherein the external electrode is connected to the plurality of electrode pads.

Assignees

• Samsung Electro Mech

Inventors

• Cho A Ra
• Shin Dong Hwi
• Yoo Seon Young

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/008 Primary

  Selection of materials · CPC title

• H01G4/005

  Electrodes · CPC title

• H01G2/065

  for surface mounting, e.g. chip capacitors · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title