Memory device and multi-pass program operation thereof

Patent metadata

Field	Value
Publication number	US-11763902-B2
Application number	US-202117483265-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Jun 25, 2021
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each target memory cell is programmed into one of K intermediate levels based on the corresponding piece of N-bits data, wherein 2N-1<K<2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the corresponding piece of N-bits data.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array having a plurality of rows of memory cells, each memory cell being configured to store a piece of N-bits data in one of 2 N levels, the level corresponding to one of 2 N pieces of N-bits data, where N is an integer greater than 1;
a plurality of word lines respectively coupled to the plurality rows of memory cells; and
a peripheral circuit coupled to the memory cell array through the word lines and configured to:
program, in a first pass, a row of target memory cells of the plurality of rows of memory cells, such that each of the row of target memory cells is programmed into one of K intermediate levels based on the corresponding piece of N-bits data to be stored in the target memory cell, wherein 2 N-1 <K<2 N ; and
program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2 N levels based on the corresponding piece of N-bits data to be stored in the target memory cell.

2. The memory device of claim 1 , wherein the peripheral circuit comprises a page buffer configured to, prior to the second pass, for each target memory cell:
read M bits of the corresponding piece of N-bits data based on the corresponding one of the K intermediate levels in which the target memory cell is programmed into in the first pass, where M is an integer smaller than N; and
receive N−M bits of the corresponding piece of N-bits data.

3. The memory device of claim 2 , wherein the page buffer is further configured to:
combine the read M bits and the received N−M bits into the corresponding piece of N-bits data; and
provide the corresponding piece of N-bits data to the target memory cell.

4. The memory device of claim 2 , wherein at least a first one of the K intermediate levels corresponds to a plurality of the 2 N pieces of N-bits data, and at least a second one of the K intermediate levels corresponds to one of the 2 N pieces of N-bits data.

5. The memory device of claim 4 , wherein the first intermediate level corresponds to two of the 2 N pieces of N-bits data.

6. The memory device of claim 5 , wherein the two pieces of N-bits data have same M bits.

7. The memory device of claim 2 , wherein N−M=1.

8. The memory device of claim 1 , wherein the peripheral circuit comprises a word line driver configured to, in the first pass:
apply a first program voltage to a selected word line of the word lines, the selected word line being coupled to the row of target memory cells; and
sequentially apply K−1 verify voltages based on the K intermediate levels to the selected word line.

9. The memory device of claim 8 , wherein the word line driver is further configured to, in the second pass:
apply a second program voltage to the selected word line; and
sequentially apply 2 N −1 verify voltages based on the 2 N levels to the selected word line.

10. The memory device of claim 1 , wherein the peripheral circuit is further configured to, between the first pass and the second pass of programming the row of target memory cells, program, in a last pass, another row of target memory cells of the plurality of rows of memory cells, the another row of target memory cells being adjacent to the row of target memory cells.

11. The memory device of claim 1 , wherein N=4, and the memory device includes a three-dimensional (3D) NAND Flash memory device.

12. A system, comprising:
a memory device configured to store data, the memory device comprising:
a memory cell array having a plurality of rows of memory cells, each memory cell being configured to store a piece of N-bits data in one of 2 N levels, the level corresponding to one of 2 N pieces of N-bits data, where N is an integer greater than 1;
a plurality of word lines respectively coupled to the plurality rows of memory cells; and
a peripheral circuit coupled to the memory cell array through the word lines and configured to:
program, in a first pass, a row of target memory cells of the plurality of rows of memory cells, such that each of the row of target memory cells is programmed into one of K intermediate levels based on the corresponding piece of N-bits data to be stored in the target memory cell, wherein 2 N-1 <K<2 N ; and
program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2 N levels based on the corresponding piece of N-bits data to be stored in the target memory cell; and

a memory controller coupled to the memory device and configured to, for each target memory cell:
transmit the corresponding piece of N-bits data to the peripheral circuit prior to the first pass;
store N−M bits of the corresponding piece of N-bits data after the first pass, where M is an integer smaller than N; and
transmit the stored N−M bits of the corresponding piece of N-bits data to the peripheral circuit prior to the second pass.

13. A method for operating a memory device, the memory device comprising a memory cell array having a plurality of rows of memory cells, and a plurality of word lines respectively coupled to the plurality rows of memory cells, the method comprising:
programming, in a first pass, a row of target memory cells of the plurality of rows of memory cells, thereby programming each of the row of target memory cells into one of K intermediate levels based on one of 2 N pieces of N-bits data to be stored in the target memory cell, where N is an integer greater than 1, wherein 2 N-1 <K<2 N ; and
programming, in a second pass after the first pass, the row of target memory cells, thereby programming each target memory cell into one of 2 N levels based on the corresponding piece of N-bits data to be stored in the target memory cell, the 2 N levels corresponding to the 2 N pieces of N-bits data.

14. The method of claim 13 , further comprising, prior to the second pass, for each target memory cell:
reading M bits of the corresponding piece of N-bits data based on the corresponding one of the K intermediate levels in which the target memory cell is programmed into in the first pass, where M is an integer smaller than N; and
receiving N−M bits of the corresponding piece of N-bits data.

15. The method of claim 14 , further comprising:
combining the read M bits and the received N−M bits into the corresponding piece of N-bits data; and
providing the corresponding piece of N-bits data to the target memory cell.

16. The method of claim 14 , wherein at least a first one of the K intermediate levels corresponds to a plurality of the 2 N pieces of N-bits data, and at least a second one of the K intermediate levels corresponds to one of the 2 N pieces of N-bits data.

17. The method of claim 16 , wherein the first intermediate level corresponds to two of the 2 N pieces of N-bits data.

18. The method of claim 17 , wherein the two pieces of N-bits data have same M bits.

19. The method of claim 14 , wherein N−M=1.

20. The method of claim 13 , wherein programming the row of target memory cells in the first pass comprises:
applying a first program voltage to a selected word line of the word lines, the selected word line being coupled to the row of target memory cells; and
sequentially applying K−1 verify voltages based on the K intermediate levels to the selected word line.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chu Ling
• Qiu Lu
• Sheng Yue

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title